Manual

234
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.6.2 DDRSDRC Refresh Timer Register
Register Name: DDRSDRC_TR
Access Type: Read/Write
Reset Value: See Table 23-8
• COUNT: DDRSDRAMC Refresh Timer Count.
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh
sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock fre-
quency (MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is pro-
grammed: (((64 x 10
-3
)/8192) x100 x10
6
= 781 or 0x030D
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– COUNT
76543210
COUNT