Manual

235
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.6.3 DDRSDRC Configuration Register
Register Name: DDRSDRC_CR
Access Type: Read/Write
Reset Value: See Table 23-8
• NC: Number of Column Bits.
The reset value is 9 column bits.
SDR-SDRAM devices with eight columns in 16-bit mode (b16mode ==1) are not supported.
• NR: Number of Row Bits
The reset value is 12 row bits.
• CAS: CAS Latency
The reset value is 2 cycles.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––DIC/DS
76543210
DLL CAS NR NC
NC DDR - Column bits SDR - Column bits
00 98
01 10 9
10 11 10
11 12 11
NR Row bits
00 11
01 12
10 13
11 14
CAS DDR-SDRAM Cas Latency SDR-SDRAM Cas Latency
000 Reserved Reserved
001 Reserved Reserved
010 22
011 33
100 Reserved Reserved