Manual

239

6264A–CAP–21-May-07

AT91CAP9S500A/AT91CAP9S250A

23.6.5 DDRSDRC Timing 1 Parameter Register

Access Type: Read/Write

Reset Value: See Table 23-8

• TRFC: row cycle delay

Reset Value is 8 cycles.

This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Num-

ber of cycles is between 0 and 31

• TXSNR: Exit self refresh delay to non read command

Reset Value is 8 cycles.

This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is

between 0 and 15. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices and

Mobile DDR-SDRAM, this field is equivalent to TXSR timing.

• TXSRD: Exit self refresh delay to Read command

Reset Value is C8.

This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between

0 and 255 cycles.This field is unique to DDR-SDRAM devices.

• TXP: Exit Power-down delay to first command

Reset Value is 3.

This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between

0 and 15 cycles. This field is unique to Mobile DDR-SDRAM devices.

31 30 29 28 27 26 25 24

–––– TXP

23 22 21 20 19 18 17 16

TXSRD

15 14 13 12 11 10 9 8

TXSNR

76543210

––– TRFC