Manual

25
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
8.2.1 External Bus Interface
The AT91CAP9S500A/AT91CAP9S250A features one External Bus Interface to offer high
bandwidth to the system and to prevent any bottleneck while accessing the external memories.
• Optimized for Application Memory Space support
• Integrates three External Memory Controllers:
– Static Memory Controller
– 4-port DDR/SDRAM Controller
– Burst/CellularRAM Controller
– ECC Controller for NAND Flash
• Additional logic for NAND Flash
and CompactFlash
• Optional Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select)
• Up to 6 chips selects, Configurable Assignment:
– Static Memory Controller on NCS0
– Burst/CellularRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
• One dedicated chip select:
– DDR/SDRAM Controller on NCS6
8.2.2 Static Memory Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
8.2.3 DDR/SDRAM Controller
• Supported devices:
– Standard and Low Power SDRAM (Mobile SDRAM)
– Mobile DDR
• Numerous configurations supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks