Manual

254
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 24-10. Burst Read Access with No Refresh Collision
Figure 24-11. Four Beat Wrapping Burst with Address Starting at 0x0C
Latency = 3
No Refresh Collision
D0 D1 D2 D3
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
BCOE
BCWE
BCOWAIT
D0 D1 D2
D3
Unwanted Data Unwanted Data
Latency = 5
Refresh Collision
Latency = 3
No Refresh Collision
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
BCOE
BCWE
BCOWAIT