Manual

288
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
buffers is a function of DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.SRC_REP,
DMAC_CTRLAx.DST_DSCR and DMAC_CFGx.DST_REP registers.
26.3.4.6 Suspension of Transfers Between buffers
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the
channel number.
Note: The buffer complete interrupt is generated at the completion of the buffer transfer to the
destination.
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
• the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’,
when n is the channel number.
26.3.4.7 Ending Multi-buffer Transfers
All multi-buffer transfers must end as shown in Row 1 of Table 26-1 on page 287. At the end of
every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
For rows 9, 10 and 11 of Table 26-1 on page 287, (DMAC_DSCRx = 0 and
DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is
disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in
the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts
the DMAC into Row 1 state.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared) the user must setup the last buffer
descriptor in memory such that both LLI.DMAC_CTRLBx.SRC_DSCR and
LLI.DMAC_CTRLBx.DST_DSCR are one and LLI.DMAC_DSCRx is set to 0.