Manual

30
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
9.5 Power Management Controller
•Provides:
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces
– the USB High-speed Device Clock UDPHSCK
– the USB Host Clock UHPCK
– independent peripheral clocks, typically at the frequency of MCK
– four programmable clock outputs: PCK0 to PCK3
• Five flexible operating modes:
– Normal Mode, processor and peripherals running at a programmable frequency
– Idle Mode, processor stopped waiting for an interrupt
– Slow Clock Mode, processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,
processor stopped waiting for an interrupt
– Backup Mode, Main Power Supplies off, VDDBU powered by a battery
Figure 9-3. AT91CAP9S500A/AT91CAP9S250A Power Management Controller Block Diagram
9.6 Periodic Interval Timer
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Includes a 12-bit Interval Overlay Counter
• Real-time OS or Linux/WinCE compliant tick generator
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,...,/64
PCK
Processor
Clock
Controller
Idle Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
USB Clock Controller
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
PLLBCK
Divider
/1,/2,/4
pck[..]
PLLBCK
PLLBCK
Divider
/1,/2,/4
ON/OFF
UHPCK
ON/OFF
DDRCK