Manual

310
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
0x07C
DMAC Channel 1 Source Picture in Picture
Configuration Register
DMAC_SPIP1 Read/Write 0x0
0x080
DMAC Channel 1 Destination Picture in Picture
Configuration Register
DMAC_DPIP1 Read/Write 0x0
0x084 Reserved – – –
0x088 Reserved – – –
0x08C DMAC Channel 2 Source Address Register DMAC_SADDR2 Read/Write 0x0
0x090 DMAC Channel 2 Destination Address Register DMAC_DADDR2 Read/Write 0x0
0x094 DMAC Channel 2 Descriptor Address Register DMAC_DSCR2 Read/Write 0x0
0x098 DMAC Channel 2 Control A Register DMAC_CTRLA2 Read/Write 0x0
0x09C DMAC Channel 2 Control B Register DMAC_CTRLB2 Read/Write 0x0
0x0A0 DMAC Channel 2 Configuration Register DMAC_CFG2 Read/Write 0x01000000
0x0A4
DMAC Channel 2 Source Picture in Picture
Configuration Register
DMAC_SPIP2 Read/Write 0x0
0x0A8
DMAC Channel 2 Destination Picture in Picture
Configuration Register
DMAC_DPIP2 Read/Write 0x0
0x0AC Reserved – – –
0x0B0 Reserved – – –
0x0B4 DMAC Channel 3 Source Address Register DMAC_SADDR3 Read/Write 0x0
0x0B8 DMAC Channel 3 Destination Address Register DMAC_DADDR3 Read/Write 0x0
0x0BC DMAC Channel 3 Descriptor Address Register DMAC_DSCR3 Read/Write 0x0
0x0C0 DMAC Channel 3 Control A Register DMAC_CTRLA3 Read/Write 0x0
0x0C4 DMAC Channel 3 Control B Register DMAC_CTRLB3 Read/Write 0x0
0x0C8 DMAC Channel 3 Configuration Register DMAC_CFG3 Read/Write 0x01000000
0x0CC
DMAC Channel 3 Source Picture in Picture
Configuration Register
DMAC_SPIP3 Read/Write 0x0
0x0D0
DMAC Channel 3 Destination Picture in Picture
Configuration Register
DMAC_DPIP3 Read/Write 0x0
0x0D4 Reserved – – –
0x0D8 Reserved – – –
0x0DC DMAC Channel 4 Source Address Register DMAC_SADDR4 Read/Write 0x0
0x0E0 DMAC Channel 4 Destination Address Register DMAC_DADDR4 Read/Write 0x0
0x0E4 DMAC Channel 4 Descriptor Address Register DMAC_DSCR4 Read/Write 0x0
0x0E8 DMAC Channel 4 Control A Register DMAC_CTRLA4 Read/Write 0x0
0x0EC DMAC Channel 4 Control B Register DMAC_CTRLB4 Read/Write 0x0
0x0F0 DMAC Channel 4 Configuration Register DMAC_CFG4 Read/Write 0x01000000
0x0F4
DMAC Channel 4 Source Picture in Picture
Configuration Register
DMAC_SPIP4 Read/Write 0x0
Table 26-2. DMAC Register Mapping
Offset Register Name Access Reset State