Manual

311
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
0x0F8
DMAC Channel 4 Destination Picture in Picture
Configuration Register
DMAC_DPIP4 Read/Write 0x0
0x0FC Reserved – – –
0x100 Reserved – – –
0x104 DMAC Channel 5 Source Address Register DMAC_SADDR5 Read/Write 0x0
0x108 DMAC Channel 5 Destination Address Register DMAC_DADDR5 Read/Write 0x0
0x10C DMAC Channel 5 Descriptor Address Register DMAC_DSCR5 Read/Write 0x0
0x110 DMAC Channel 5 Control A Register DMAC_CTRLA5 Read/Write 0x0
0x114 DMAC Channel 5 Control A Register DMAC_CTRLB5 Read/Write 0x0
0x118 DMAC Channel 5 Configuration Register DMAC_CFG5 Read/Write 0x01000000
0x11C
DMAC Channel 5 Source Picture in Picture
Configuration Register
DMAC_SPIP5 Read/Write 0x0
0x120
DMAC Channel 5 Destination Picture in Picture
Configuration Register
DMAC_DPIP5 Read/Write 0x0
0x124 Reserved – – –
0x128 Reserved – – –
0x12C DMAC Channel 6 Source Address Register DMAC_SADDR6 Read/Write 0x0
0x130 DMAC Channel 6 Destination Address Register DMAC_DADDR6 Read/Write 0x0
0x134 DMAC Channel 5 Descriptor Address Register DMAC_DSCR6 Read/Write 0x0
0x138 DMAC Channel 6 Control A Register DMAC_CTRLA6 Read/Write 0x0
0x13C DMAC Channel 6 Control B Register DMAC_CTRLB6 Read/Write 0x0
0x140 DMAC Channel 6 Configuration Register DMAC_CFG6 Read/Write 0x01000000
0x144
DMAC Channel 6 Source Picture in Picture
Configuration Register
DMAC_SPIP6 Read/Write 0x0
0x148
DMAC Channel 6 Destination Picture in Picture
Configuration Register
DMAC_DPIP6 Read/Write 0x0
0x14C Reserved – – –
0x150 Reserved – – –
0x154 DMAC Channel 7 Source Address Register DMAC_SADDR7 Read/Write 0x0
0x158 DMAC Channel 7 Destination Address Register DMAC_DADDR7 Read/Write 0x0
0x15C DMAC Channel 7 Descriptor Address Register DMAC_DSCR7 Read/Write 0x0
0x160 DMAC Channel 7 Control A Register DMAC_CTRLA7 Read/Write 0x0
0x164 DMAC Channel 7 Control B Register DMAC_CTRLB7 Read/Write 0x0
0x168 DMAC Channel 7 Configuration Register DMAC_CFG7 Read/Write 0x01000000
0x16C
DMAC Channel 7 Source Picture in Picture
Configuration Register
DMAC_SPIP7 Read/Write 0x0
0x170
DMAC Channel 7 Destination Picture in Picture
Configuration Register
DMAC_DPIP7 Read/Write 0x0
Table 26-2. DMAC Register Mapping
Offset Register Name Access Reset State