Manual

314
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
26.5.2 DMAC Enable Register
Name: DMAC_EN
Access: Read/Write
Reset Value: 0x00000000
• ENABLE
0: DMA Controller is disabled.
1: DMA Controller is enabled.
26.5.3 DMAC Software Single Request Register
Name: DMAC_SREQ
Access: Read/Write
Reset Value: 0x00000000
• DSREQ[i]
Request a destination single transfer on channel i.
• SSREQ[i]
Request a source single transfer on channel i.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
–––––––ENABLE
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
DSREQ3 SSREQ3 DSREQ2 SSREQ2 DSREQ1 SSREQ1 DSREQ0 SSREQ0