Manual

324
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
26.5.14 DMAC Channel x [x = 0..3] Destination Address Register
Name: DMAC_DADDRx [x = 0..3]
Access: Read/Write
Reset Value: 0x00000000
• DADDRx
Channel x destination address. This register must be aligned with the destination transfer width.
31 30 29 28 27 26 25 24
DADDRx
23 22 21 20 19 18 17 16
DADDRx
15 14 13 12 11 10 9 8
DADDRx
76543210
DADDRx