Manual

329
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
• DST_DSCR
0: Destination address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the destination.
•FC
This field defines which devices controls the size of the buffer transfer, also referred as to the Flow Controller.
•SRC_INCR
• DST_INCR
•AUTO
Automatic multiple buffer transfer is enabled. When set, this bit enables replay mode or contiguous mode when several
buffers are transferred.
FC Type of transfer Flow Controller
000 Memory-to-Memory DMA Controller
001 Memory-to-Peripheral DMA Controller
010 Peripheral-to-Memory DMA Controller
011 Peripheral-to-Peripheral DMA Controller
100 Peripheral-to-Memory Peripheral
101 Memory-to-Peripheral Peripheral
110 Peripheral-to-Peripheral Source Peripheral
111 Peripheral-to-Peripheral Destination Peripheral
SRC_INCR Type of addressing mode
00 INCREMENTING
01 DECREMENTING
10 FIXED
DST_INCR Type of addressing scheme
00 INCREMENTING
01 DECREMENTING
10 FIXED