Manual

34
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
10.2.1 Peripheral Interrupts and Clock Control
10.2.1.1 System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the DDR/SDRAM Controller
• the BCRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-Time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
• the MP Block
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.2.1.2 External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
10.2.1.3 Timer Counter Interrupts
The three Timer Counter channels interrupt signals are OR-wired together to provide the inter-
rupt source 19 of the Advanced Interrupt Controller. This forces the programmer to read all
Timer Counter status registers before branching the right Interrupt Service Routine.
The Timer Counter channels clocks cannot be deactivated independently. Switching off the
clock of the Peripheral 19 disables the clock of the 3 channels.
24 ADCC ADC Controller
25 ISI Image Sensor Interface
26 LCDC LCD Controller
27 DMA DMA Controller
28 UDPHS USB High Speed Device Port
29 UHP USB Host Port
30 AIC Advanced Interrupt Controller IRQ0
31 AIC Advanced Interrupt Controller IRQ1
Table 10-1. AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers (Continued)
Peripheral
ID
Peripheral
Mnemonic Peripheral Name
External
Interrupt