Manual

349
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
28. Clock Generator
28.1 Description
The Clock Generator is made up of 2 PLLs, a Main Oscillator, and a 32,768 Hz low-power
Oscillator.
It provides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Oscillator
The Clock Generator User Interface is embedded within the Power Management Controller one
and is described in Section 29.9. However, the Clock Generator registers are named CKGR_.
• PLLACK is the output of the Divider and PLL A block
• PLLBCK is the output of the Divider and PLL B block
28.2 Slow Clock Crystal Oscillator
The Clock Generator integrates a 32,768 Hz low-power oscillator. The XIN32 and XOUT32 pins
must be connected to a 32,768 Hz crystal. Two external capacitors must be wired as shown in
Figure 28-1.
Figure 28-1. Typical Slow Clock Crystal Oscillator Connection
28.3 Main Oscillator
Figure 28-2 shows the Main Oscillator block diagram.
XIN32 XOUT32 GNDPLL
32,768 Hz
Crystal