Manual

43
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
10.4.10 USB Host Port
Compliance with OHCI Rev 1.0 Specification
Compliance with USB V2.0 Full-speed and Low-speed Specification
Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps devices
Root hub integrated with two downstream USB ports
Two embedded USB transceivers
Supports power management
Operates as a master on the Matrix
Internal DMA Controller, operating as a Master on Bus Matrix
10.4.11 USB High Speed Device Port
USB V2.0 high-speed compliant, 480 MBits per second
Embedded USB V2.0 UTMI+ high-speed transceiver
Embedded 4K-byte dual-port RAM for endpoints
Embedded 6 channels DMA controller
Suspend/Resume logic
Up to 2 or 3 banks for isochronous and bulk endpoints
Seven endpoints:
Endpoint 0: 64 bytes, 1 bank mode
Endpoint 1 & 2: 512 bytes, 2 banks mode, HS isochronous capable
Endpoint 3 & 4: 64 bytes, 3 banks mode
Endpoint 5 & 6: 1024 bytes, 3 banks mode, HS isochronous capable
10.4.12 LCD Controller
Single and Dual scan color and monochrome passive STN LCD panels supported
Single scan active TFT LCD panels supported
4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
Up to 24-bit single scan TFT interfaces supported
Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
Single clock domain architecture
Resolution supported up to 2048x2048
2D-DMA Controller for management of virtual Frame Buffer
Allows management of frame buffer larger than the screen size and moving the view
over this virtual frame buffer
Automatic resynchronization of the frame buffer pointer to prevent flickering
10.4.13 Ethernet 10/100 MAC
Compatibility with IEEE Standard 802.3
10 and 100 MBits per second data throughput capability