Manual

6264A–CAP–21-May-07

AT91CAP9S500A/AT91CAP9S250A

• Full- and half-duplex operations

• MII or RMII interface to the physical layer

• Register Interface to address, data, status and control registers

• Internal DMA Controller, operating as a Master on Bus Matrix

• Interrupt generation to signal receive and transmit completion

• 28-byte transmit and 28-byte receive FIFOs

• Automatic pad and CRC generation on transmitted frames

• Address checking logic to recognize four 48-bit addresses

• Support promiscuous mode where all valid frames are copied to memory

• Support physical layer management through MDIO interface control of alarm and update

time/calendar data in

10.4.14 Image Sensor Interface

• ITU-R BT. 601/656 8-bit mode external interface support

• Support for ITU-R BT.656-4 SAV and EAV synchronization

• Vertical and horizontal resolutions up to 2048 x 2048

• Preview Path up to 640*480

• Support for packed data formatting for YCbCr 4:2:2 formats

• Preview scaler to generate smaller size image

• Programmable frame capture rate

• Internal DMA Controller, operating as a Master on Bus Matrix