Manual

46
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
• 30 or 60 MHz UTMI+ USB Clock
• MCK System Clock
• DDRCK Dual Rate System Clock
• PCK Processor Clock
• 5 Gated Peripherals Clock (for AHB and/or APB peripherals) corresponding to Peripheral ID
3 to 7
11.1.2 AHB Master Buses
The MPBlock may implement up to three AHB masters, each having a dedicated AHB master
bus connected to the Bus Matrix.
11.1.3 AHB Slave Buses
The MPBlock receives four different AHB slave buses coming from the Bus Matrix. Each bus
has two or four select signals that can implement up to 12 AHB slaves.
11.1.4 Interrupts
The MPBlock is connected to 5 dedicated interrupt lines corresponding to Peripheral ID 3 to 9.
It is also connected to two other interrupt lines (through OR gate) corresponding to Peripheral ID
1 and 2
11.1.5 DMA Channels
The MPBlock is connected to 4 DMA hardware handshaking interfaces, allowing it to implement
up to 4 DMA enabled peripherals.
11.1.6 Peripheral DMA Channels
The MPBlock is not connected to the Peripheral DMA Controller. In order to implement Periph-
eral DMA Controller (PDC) enabled APB peripherals, a PDC and an AHB-to-APB Bridge must
be integrated into the MPBlock using one AHB master and one AHB slave bus.
11.1.7 MPBlock Single Port RAMs
The MPBlock is connected to eight instances of 512x72 High-Speed Single Port RAMs.
The MPBlock has control over all memory connections.
11.1.8 MPBlock Dual Port RAMs
The MPBlock is connected to ten instances of 512x36 High-Speed Dual Port RAMs.
The MPBlock has control over all memory connections.
11.1.9 Optional Peripherals Enable
The MPBlock drives the enable of the optional peripherals, and so can enable or disable any of
the optional peripherals.