Manual

493

6264A–CAP–21-May-07

AT91CAP9S500A/AT91CAP9S250A

34.7.8 Read/Write Flowcharts

The following flowcharts shown in Figure 34-14, Figure 34-15 on page 494, Figure 34-16 on

page 495, Figure 34-17 on page 496, Figure 34-18 on page 497 and Figure on page 497 give

examples for read and write operations. A polling or interrupt method can be used to check the

status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be config-

ured first.

Figure 34-14. TWI Write Operation with Single Data Byte without Internal Address

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address (DADR)

- Transfer direction bit

Write ==> bit MREAD = 0

Load Transmit register

TWI_THR = Data to send

Read Status register

TXRDY = 1?

Read Status register

TXCOMP = 1?

Transfer finished

Ye s

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