Manual

510
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
34.10 Two-wire Interface (TWI) User Interface
Table 34-5. Two-wire Interface (TWI) User Interface
Offset Register Name Access Reset State
0x00 Control Register TWI_CR Write-only N / A
0x04 Master Mode Register TWI_MMR Read/Write 0x00000000
0x08 Slave Mode Register TWI_SMR Read/Write 0x00000000
0x0C Internal Address Register TWI_IADR Read/Write 0x00000000
0x10 Clock Waveform Generator Register TWI_CWGR Read/Write 0x00000000
0x20 Status Register TWI_SR Read-only 0x0000F009
0x24 Interrupt Enable Register TWI_IER Write-only N / A
0x28 Interrupt Disable Register TWI_IDR Write-only N / A
0x2C Interrupt Mask Register TWI_IMR Read-only 0x00000000
0x30 Receive Holding Register TWI_RHR Read-only 0x00000000
0x34 Transmit Holding Register TWI_THR Write-only 0x00000000
0x38 - 0xFC Reserved – – –
0x100 - 0x124 Reserved for the PDC – – –