Manual

517
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
34.10.6 TWI Status Register
Name: TWI_SR
Access: Read-only
Reset Value: 0x0000F009
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode
:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in Figure 34-8 on page 488 and in Figure 34-10 on page 489.
TXCOMP used in Slave mode
:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Figure 34-27 on page 506, Figure 34-28 on page 507, Figure 34-29 on
page 508 and Figure 34-30 on page 508.
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in Figure 34-10 on page 489.
RXRDY behavior in Slave mode can be seen in Figure 34-25 on page 504, Figure 34-28 on page 507, Figure 34-29 on
page 508 and Figure 34-30 on page 508.
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode
:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in Figure 34-8 on page 488.
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TXBUFE RXBUFF ENDTX ENDRX EOSACC SCLWS ARBLST NACK
76543210
– OVRE GACC SVACC SVREAD TXRDY RXRDY TXCOMP