Manual

58
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
12.4 CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the
items in the list below:
• ARM9EJ-S
• Caches (ICache, DCache and write buffer)
•TCM
•MMU
• Other system options
To control these features, CP15 provides 16 additional registers. See Table 12-5.
LSL Logical Shift Left LSR Logical Shift Right
ASR Arithmetic Shift Right ROR Rotate Right
MUL Multiply BLX Branch, Link, and Exchange
B Branch BL Branch and Link
BX Branch and Exchange SWI Software Interrupt
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRSH Load Signed Halfword LDRSB Load Signed Byte
LDMIA Load Multiple STMIA Store Multiple
PUSH Push Register to stack POP Pop Register from stack
BCC Conditional Branch BKPT Breakpoint
Table 12-4. Thumb Instruction Mnemonic List (Continued)
Mnemonic Operation Mnemonic Operation
Table 12-5. CP15 Registers
Register Name Read/Write
0 ID Code
(1)
Read/Unpredictable
0 Cache type
(1)
Read/Unpredictable
0 TCM status
(1)
Read/Unpredictable
1 Control Read/write
2 Translation Table Base Read/write
3 Domain Access Control Read/write
4 Reserved None
5 Data fault Status
(1)
Read/write
5 Instruction fault status
(1)
Read/write
6 Fault Address Read/write
7 Cache Operations Read/Write
8 TLB operations Unpredictable/Write