Manual

755
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
40.6.10 PWM Channel Duty Cycle Register
Register Name: PWM_CDTYx
Access Type: Read/Write
Only the first 16 bits (internal channel counter size) are significant.
• CDTY: Channel Duty Cycle
Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
31 30 29 28 27 26 25 24
CDTY
23 22 21 20 19 18 17 16
CDTY
15 14 13 12 11 10 9 8
CDTY
76543210
CDTY