Manual
874
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
44.5 USB High Speed Device Port (UDPHS) User Interface
Notes: 1. The reset value for UDPHS_EPTCTL0 is 0x0000_0001.
2. The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group of reg-
isters is repeated successively for each endpoint according to the consecution of endpoint registers located between 0x120
and
0x1FC.
3. The addresses for the UDPHS DMA registers shown here are for UDPHS DMA Channel1. (There is no Channel0) The
structure of this group of registers is repeated successively for each DMA channel according to the consecution of DMA reg-
isters located between 0x320 and 0x36C.
Table 44-5. Register Mapping
Offset Register Name Access Reset
0x00 UDPHS Control Register UDPHS_CTRL Read/Write 0x0000_0200
0x04 UDPHS Frame Number Register UDPHS_FNUM Read 0x0000_0000
0x08 - 0x0C Reserved – – –
0x10 UDPHS Interrupt Enable Register UDPHS_IEN Read/Write 0x0000_0010
0x14 UDPHS Interrupt Status Register UDPHS_INTSTA Read 0x0000_0000
0x18 UDPHS Clear Interrupt Register UDPHS_CLRINT Write –
0x1C UDPHS Endpoints Reset Register UDPHS_EPTRST Write –
0x20 - 0xCC Reserved – – –
0xE0 UDPHS Test Register UDPHS_TST Read/Write 0x0000_0000
0xE4 - 0xE8 Reserved – – –
0x100 UDPHS Endpoint0 Configuration Register UDPHS_EPTCFG0 Read/Write 0x0000_0000
0x104 UDPHS Endpoint0 Control Enable Register UDPHS_EPTCTLENB0 Write –
0x108 UDPHS Endpoint0 Control Disable Register UDPHS_EPTCTLDIS0 Write –
0x10C UDPHS Endpoint0 Control Register UDPHS_EPTCTL0 Read 0x0000_0000
(1)
0x110 Reserved (for endpoint 0) – – –
0x114 UDPHS Endpoint0 Set Status Register UDPHS_EPTSETSTA0 Write –
0x118 UDPHS Endpoint0 Clear Status Register UDPHS_EPTCLRSTA0 Write –
0x11C UDPHS Endpoint0 Status Register UDPHS_EPTSTA0 Read 0x0000_0040
0x120 - 0x1FC UDPHS Endpoint1 to 7
(2)
Registers
0x200 - 0x300 Reserved – – –
0x300 - 0x30C Reserved – – –
0x310 UDPHS DMA Next Descriptor1 Address Register UDPHS_DMANXTDSC1 Read/Write 0x0000_0000
0x314 UDPHS DMA Channel1 Address Register UDPHS_DMAADDRESS1 Read/Write 0x0000_0000
0x318 UDPHS DMA Channel1 Control Register UDPHS_DMACONTROL1 Read/Write 0x0000_0000
0x31C UDPHS DMA Channel1 Status Register UDPHS_DMASTATUS1 Read/Write 0x0000_0000
0x320 - 0x36C DMA Channel2 to 6
(3)
Registers