Manual

922
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
45.4.1 ISI Control 1 Register
Register Name: ISI_CR1
Access Type: Read/Write
Reset Value: 0x00000002
• ISI_RST: Image sensor interface reset
Write-only. Refer to bit SOFTRST in Section 45.4.3 ”ISI Status Register” on page 926 for soft reset status.
0: No action
1: Resets the image sensor interface.
• ISI_DIS: Image sensor disable:
0: Enable the image sensor interface.
1: Finish capturing the current frame and then shut down the module.
• HSYNC_POL: Horizontal synchronization polarity
0: HSYNC active high
1: HSYNC active low
• VSYNC_POL: Vertical synchronization polarity
0: VSYNC active high
1: VSYNC active low
• PIXCLK_POL: Pixel clock polarity
0: Data is sampled on rising edge of pixel clock
1: Data is sampled on falling edge of pixel clock
• EMB_SYNC: Embedded synchronization
0: Synchronization by HSYNC, VSYNC
1: Synchronization by embedded synchronization sequence SAV/EAV
• CRC_SYNC: Embedded synchronization
0: No CRC correction is performed on embedded synchronization
31 30 29 28 27 26 25 24
SFD
23 22 21 20 19 18 17 16
SLD
15 14 13 12 11 10 9 8
CODEC_ON THMASK FULL - FRATE
76543210
CRC_SYNC EMB_SYNC - PIXCLK_POL VSYNC_POL HSYNC_POL ISI_DIS ISI_RST