Manual

974
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 47-5. SDRAMC Timings
The timings of the SDRAM controller support the use of PC100, PC133 (3.3V supply) and of
Mobile SDRAM (1.8 supply) in MAX and STH corners.
Data In
SDCK
Data Out
SDRAMC1 SDRAMC2SDRAMC1 SDRAMC2
Control, Address
SDRAMC3 SDRAMC4
SDRAMC1 SDRAMC2
Table 47-29. SDRAM PC100 Characteristics
Parameter
Min Max
Unit3.3V Supply 3.3V Supply
SDRAM Controller Clock Frequency 100 MHz
Control/Address/Data In Setup
(1)
2ns
Control/Address/Data In Hold
(1)
1ns
Data Out Access time after SDCK rising 6 ns
Data Out Change time after SDCK rising 3 ns
Table 47-30. SDRAM PC133 Characteristics
Parameter
Min Max
Unit3.3V Supply 3.3V Supply
SDRAM Controller Clock Frequency 133 MHz
Control/Address/Data In Setup
(1)
1.5 ns
Control/Address/Data In Hold
(1)
0.8 ns
Data Out Access time after SDCK rising 5.4 ns
Data Out Change time after SDCK rising 3.0 ns