Manual

i
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Table of Contents
Features .........................................................................................1
1 Description ...................................................................................3
2 AT91CAP9S500A/AT91CAP9S250A Block Diagram .................4
3 Signal Description .......................................................................5
4 Package and Pinout ...................................................................10
4.1 400-ball BGA Package Outline ...............................................................10
4.2 400-ball BGA Package Pinout ...............................................................11
5 Power Considerations ...............................................................13
5.1 Power Supplies ......................................................................................13
5.2 Power Consumption ...............................................................................14
5.3 Programmable I/O Lines Power Supplies ...............................................14
6 I/O Line Considerations .............................................................15
6.1 JTAG Port Pins .......................................................................................15
6.2 Test Pin ..................................................................................................15
6.3 Reset Pins ..............................................................................................15
6.4 PIO Controllers .......................................................................................15
6.5 Shutdown Logic Pins ..............................................................................15
7 Processor and Architecture ......................................................16
7.1 ARM926EJ-S Processor ........................................................................16
7.2 Bus Matrix ..............................................................................................16
7.3 Matrix Masters ........................................................................................17
7.4 Matrix Slaves ..........................................................................................17
7.5 Master-to-Slave Access .........................................................................18
7.6 Peripheral DMA Controller .....................................................................20
7.7 DMA Controller .......................................................................................20
7.8 Debug and Test Features .......................................................................21
8 Memories ....................................................................................22
8.1 Embedded Memories .............................................................................23
8.2 External Memories .................................................................................24
9 System Controller ......................................................................27
9.1 System Controller Block Diagram ...........................................................28