Owner's manual

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Features

• Low-voltage and Standard-voltage Operation

–2.7(V

=2.7Vto5.5V)

• User Selectable Internal Organization

– 16K:2048x8or1024 x 16

• 3-wire Serial Interface

• Sequential Read Operation

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• 2 MHz Clock Rate (5V) Compatibility

• Self-timed Write Cycle (10 ms max)

• High Reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages

Description

The AT93C86 provides 16384 bits of serial electrically erasable programmable read

only memory (EEPROM) organized as 1024 words of 16 bits each when the ORG Pin

is connected to V

and 2048 words of 8 bits each when it is tied to ground. The

device is optimized for use in many industrial and commercial applications where low

power and low voltage operations are essential. The AT93C86 is available in space

saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages.

The AT93C86 is enabled through the Chip Select pin (CS), and accessed via a 3-wire

serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK).

3-wire Serial

EEPROM

16K (2048 x 8 or 1024 x 16)

AT93C86

Rev. 1237D–SEEPR–08/02

Pin Configurations

Pin Name Function

CS Chip Select

SK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

GND Ground

VCC Power Supply

ORG Internal Organization

DC Don’t Connect

8-lead PDIP

VCC

ORG

GND

8-lead SOIC

VCC

ORG

GND

(continued)

8-lead TSSOP

VCC

ORG

GND

Summary of content (15 pages)

PAGE 1
Features • Low-voltage and Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.
PAGE 2
Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought “high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY status of the part. The AT93C86 is available in a 2.7V to 5.5V version.
PAGE 3
AT93C86 Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Symbol Test Conditions COUT CIN Note: Max Units Conditions Output Capacitance (DO) 5 pF VOUT = 0V Input Capacitance (CS, SK, DI) 5 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V, TAC = 0°C to +70°C, VCC = +2.7V to +5.
PAGE 4
AC Characteristics Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Test Condition fSK SK Clock Frequency 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 0 0 tSKH SK High Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tSKL SK Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tCS Minimum CS Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.
PAGE 5
AT93C86 Instruction Set for the AT93C86 Address Instruction Data SB Op Code x8 x 16 READ 1 10 A10 - A0 A9 - A0 Reads data stored in memory, at specified address. EWEN 1 00 11XXXXXXXX 11XXXXXXXX Write enable must precede all programming modes.
PAGE 6
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction.
PAGE 7
AT93C86 Timing Diagrams Synchronous Data Timing Note: 1. This is the minimum SK period.
PAGE 8
READ Timing tCS High Impedance EWEN Timing tCS CS SK DI 1 0 0 1 1 ... EWDS Timing tCS CS SK DI 8 1 0 0 0 0 ...
PAGE 9
AT93C86 WRITE Timing tCS CS SK DI DO 1 0 1 AN ... A0 DN ... D0 HIGH IMPEDANCE BUSY READY tWP WRAL Timing(1) tCS CS SK DI DO 1 0 0 0 1 ... DN ... D0 BUSY HIGH IMPEDANCE READY tWP Note: 1. Valid only at VCC = 4.5V to 5.5V.
PAGE 10
ERASE Timing tCS CS STANDBY CHECK STATUS SK DI 1 1 1 AN AN-1 AN-2 ... A0 tDF tSV HIGH IMPEDANCE DO HIGH IMPEDANCE BUSY READY tWP ERAL Timing(1) tCS CS CHECK STATUS STANDBY tSV tDF SK DI DO 1 0 0 1 0 BUSY HIGH IMPEDANCE HIGH IMPEDANCE READY tWP Note: 10 1. Valid only at VCC = 4.5V to 5.5V.
PAGE 11
AT93C86 AT93C86 Ordering Information Ordering Code Package AT93C86-10PI-2.7 AT93C86-10SI-2.7 AT93C86-10TI-2.7 8P3 8S1 8A2 Note: Operation Range Industrial (-40°C to 85°C) For 2.7V devices used in a 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.
PAGE 12
Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 b3 b 4 PLCS Side View L Notes: 0.210 0.100 BSC eA 0.300 BSC 0.115 NOTE 2 3 3 e L MAX 0.130 4 0.150 2 1.
PAGE 13
AT93C86 8S1 – JEDEC SOIC 3 2 1 H N Top View e B A D COMMON DIMENSIONS (Unit of Measure = mm) Side View A2 C L SYMBOL MIN NOM MAX A – – 1.75 B – – 0.51 C – – 0.25 D – – 5.00 E – – 4.00 e E End View NOTE 1.27 BSC H – – 6.20 L – – 1.27 Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 10/10/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.
PAGE 14
8A2 – TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A b D MIN NOM MAX NOTE 2.90 3.00 3.10 2, 5 3, 5 E e D A2 6.40 BSC E1 4.30 4.40 4.50 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 e Side View L 0.65 BSC 0.45 L1 Notes: 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2.
PAGE 15
Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.