Features • • • • • • • • • • • • • • • • • • • Master and Slave Operation Possible Supply Voltage up to 40V Operating voltage VS = 5V to 27V Typically 10 µA Supply Current During Sleep Mode Typically 40 µA Supply Current in Silent Mode Linear Low-drop Voltage Regulator: – Normal, Fail-safe, and Silent Mode • ATA6628 VCC = 3.3V ±2% • ATA6630 VCC = 5.
Figure 1-1. Block Diagram 20 VS 11 INH PVCC 5k Normal and Fail-safe Mode Normal and Fail-safe Mode Receiver 7 RXD 6 RF Filter LIN 4 WAKE 17 KL_15 PVCC 12 TXD Edge Detection Wake-up Bus Timer Slew Rate Control TXD Time-out Timer Control Unit 2 EN 10 SP_MODE Short Circuit and Overtemperature Protection Debounce Time Mode Select Normal/Silent/ Fail-safe Mode 3.
ATA6628/ATA6630 [Preliminary] 2. Pin Configuration VBATT VCC PVCC KL15 MODE Pinning QFN20 VS Figure 2-1. 20 19 18 17 16 1 15 TM 14 WD_OSC 13 NRES 12 TXD 11 INH ATA6628/30 Table 2-1. 4 GND 5 6 7 8 9 10 SP_MODE WAKE QFN 5 mm 5 mm 0.
3. Functional Description 3.1 Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions. 3.2 Supply Pin (VS) The LIN operating voltage is VS = 5V to 27V.
ATA6628/ATA6630 [Preliminary] 3.7 Input/Output Pin (TXD) In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or not connected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output and is signalling the fail-safe source. It is current-limited to < 8 mA. 3.
3.13 TM Input Pin The TM pin is used for final production measurements at Atmel®. In normal application, it has to be always connected to GND. 3.14 KL_15 Pin The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It is an edge-sensitive pin (low-to-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on.
ATA6628/ATA6630 [Preliminary] 3.20 DIV_ON Input Pin The DIV_ON pin is a low voltage input. It is used to switch on or off the internal voltage divider PV output directly with no time limitation (see Table 3-1 on page 7). It is switched on if DIV_ON is high or it is switched off if DIV_ON is low. In Sleep Mode the DIV_ON functionality is disabled and PV is off. An internal pull-down resistor is implemented. 3.21 VBATT Input Pin The VBATT is a high voltage input pin to supply the internal voltage divider.
4. Modes of Operation Figure 4-1. Modes of Operation a: VS > VSthF Unpowered Mode (See Section 4.5) b b: VS < VSthU c: Bus wake-up event d: Wake up from WAKE or KL_15 pin a e: NRES switches to low b Fail-safe Mode VCC: 3.3V/5V/50 mA with undervoltage monitoring Communication: OFF Watchdog: ON b e EN = 1 b c+d+e EN = 1 c+d Go to silent command EN = 0 Normal Mode VCC: 3.
ATA6628/ATA6630 [Preliminary] 4.1 Normal Mode This is the normal transmitting and receiving mode. The voltage regulator is active and can source up to 50 mA. The undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode. 4.2 Silent Mode A falling edge at EN when TXD is high switches the IC into Silent Mode.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (tbus) and the following rising edge at the LIN pin (see Figure 4-3 on page 10) result in a remote wake-up request. The device switches from Silent Mode to Fail-safe Mode. The internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 4-3 on page 10).
ATA6628/ATA6630 [Preliminary] 4.3 Sleep Mode A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 4-4 on page 11). In order to avoid any influence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2 µs earlier to Low than the TXD. Therefore, the best an easiest way are two falling edges at TXD and EN at the same time. The transmission path is disabled in Sleep Mode.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t bus ) and a rising edge at pin LIN result in a remote wake-up request. The device switches from Sleep Mode to Fail-safe Mode. The VCC regulator is activated, and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 4-5 on page 12).
ATA6628/ATA6630 [Preliminary] 4.4 Sleep or Silent Mode: Behavior at a Floating LIN-bus or a Short Circuited LIN to GND In Sleep or in Silent Mode the device has a very low current consumption even during shortcircuits or floating conditions on the bus. A floating bus can arise if the Master pull-up resistor is missing, e.g., if it is switched off when the LIN- Master is in sleep mode or even if the power supply of the Master node is switched off.
Figure 4-7. Short Circuit to GND on the LIN bus During Sleep- or Silent Mode LIN Pre-wake LIN BUS VLINL LIN dominant state VBUSdom tmon tmon IVS Mode of operation Int.
ATA6628/ATA6630 [Preliminary] 4.5 Fail-safe Mode The device automatically switches to Fail-safe Mode at system power-up. The voltage regulator is switched on (VCC = 3.3V/5V/2%/50 mA) (see Figure 5-1 on page 19). The NRES output switches to low for tres = 4 ms and gives a reset to the microcontroller. LIN communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal Mode.
4.6 Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 5-1 on page 19). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the VCC capacitor and the load. The NRES is low for the reset time delay treset .
ATA6628/ATA6630 [Preliminary] 5. Wake-up Scenarios from Silent or Sleep Mode 5.1 Remote Wake-up via Dominant Bus State A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (tBUS) and a rising edge at pin LIN result in a remote wake-up request. The device switches from Silent or Sleep Mode to Fail-safe Mode.
5.5 Fail-safe Features • During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator works independently.
ATA6628/ATA6630 [Preliminary] 5.6 Voltage Regulator The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. The main power dissipation of the IC is created from the VCC output current IVCC , which is needed for the application.
6. Watchdog The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window of T w d . The trigger signal must exceed a minimum time ttrigmin > 200 ns. If a triggering signal is not received, a reset signal will be generated at output NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor Rwd_osc (34 kΩ to 120 kΩ).
ATA6628/ATA6630 [Preliminary] Figure 6-1. Timing Sequence with RWD_OSC = 51 kΩ VCC 3.3V 5V Undervoltage Reset NRES Watchdog Reset tnres = 4 ms treset = 4 ms td = 155 ms t1 t1 = 20.6 ms t2 t2 = 21 ms twd NTRIG ttrig > 200 ns 6.2 Worst Case Calculation with RWD_OSC = 51 kΩ The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%. The worst case calculation for the watchdog period twd is calculated as follows.
7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Supply voltage VS VS –0.
ATA6628/ATA6630 [Preliminary] 8. Thermal Characteristics Parameters Symbol Thermal resistance junction to heat slug Rthjc Thermal resistance junction to ambient, where heat slug is soldered to PCB according to Jedec Rthja Min. Typ. Max. Unit 10 K/W 35 K/W Thermal shutdown of VCC regulator 150 165 170 °C Thermal shutdown of LIN output 150 165 170 °C Thermal shutdown hysteresis 10 °C 9. Electrical Characteristics 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified.
9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. 2 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.3 2.5 8 mA A 0.4 V A 7 kΩ A RXD Output Pin 2.1 Low-level output sink current Normal Mode VLIN = 0V VRXD = 0.4V RXD IRXD 2.2 Low-level output voltage IRXD = 1 mA RXD VRXDL 2.3 Internal resistor to PVCC RXD RRXD 3 TXD VTXDL –0.3 +0.8 V A VCC + 0.
ATA6628/ATA6630 [Preliminary] 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol 8.3 Driver dominant voltage VVS = 18V Rload = 500 Ω LIN V_HiSUP 8.4 Driver dominant voltage VVS = 7.0V Rload = 1000 Ω LIN V_LoSUP_1k 8.5 Driver dominant voltage VVS = 18V Rload = 1000 Ω LIN 8.6 Pull-up resistor to VS The serial diode is mandatory 8.7 Max. Unit Type* 2 V A 0.
9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Pin Symbol Min. Typ. Max. Unit Type* Time delay for mode 10.2 change from Fail-safe into VEN = VCC Normal Mode via EN pin EN tnorm 5 15 20 µs A Time delay for mode change from Normal 10.3 Mode to Sleep Mode via EN pin VEN = 0V EN tsleep 2 7 12 µs A VTXD = 0V TXD tdom 27 55 70 ms A Time delay for mode 10.
ATA6628/ATA6630 [Preliminary] 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions 12 NRES Open Drain Output Pin Pin Symbol Min. Typ. Max. Unit Type* 12.1 Low-level output voltage VS ≥ 5.5V INRES = 1 mA INRES = 250 µA NRES VNRESL 0.2 0.14 V V A 12.2 Low-level output low 10 kΩ to VCC VCC = 0V NRES VNRESLL 0.2 V A 12.3 Undervoltage reset time VS ≥ 5.
9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters 17 VCC Voltage Regulator ATA6628 in Normal/Fail-safe and Silent Mode, VCC and PVCC Short-circuited 17.1 Output voltage VCC 17.2 Test Conditions 4V < VS < 18V (0 mA to 50 mA) Output voltage VCC at low 3V < VS < 4V VS Pin Symbol Min. 3.366 V A VCC VCClow VS – VD 3.366 V A VS, VCC VD VS > 3V, IVCC = –50 mA VS, VCC VD 17.
ATA6628/ATA6630 [Preliminary] 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters 19 DIV_ON Input Pin Test Conditions 19.1 Low-level voltage input 19.2 High-level voltage input Pin Symbol Min. DIV_ON VDIV_ON –0.3 DIV_ON VDIV_ON 2 19.3 Pull-down resistor VDIV_ON = VCC DIV_ON RDIV_ON 125 19.4 Low-level input current VDIV_ON = 0V DIV_ON IDIV_ON –3 20 Typ. 250 Max. Unit Type* +0.
Figure 9-1.
ATA6628/ATA6630 [Preliminary] Figure 9-2. Application Circuit Ignition KL15 VBattery debug KL30 100 nF 47 kΩ 10 nF 20 2.7 kΩ Wake switch WAKE GND MODE 15 ATA6628 ATA6630 2 14 MLP 5 mm 5 mm 0.
10. Ordering Information Extended Type Number Package Remarks ATA6628-PGPW QFN20 3.3V LIN system-basis-chip, Pb-free, 1.5k, taped and reeled ATA6630-PGPW QFN20 5V LIN system-basis-chip, Pb-free, 1.5k, taped and reeled ATA6628-PGQW QFN20 3.3V LIN system-basis-chip, Pb-free, 6k, taped and reeled ATA6630-PGQW QFN20 5V LIN system-basis-chip, Pb-free, 6k, taped and reeled 11. Package Information Package: VQFN_5 x 5_20L Exposed pad 3.1 x 3.1 Dimensions in mm Not indicated tolerances ±0.
ATA6628/ATA6630 [Preliminary] 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9117C-AUTO-10/09 • Complete datasheet: “LIN 2.1 specicfication” changed in “LIN 2.0, 2.1 specicfication or “2.x” • Features on page 1 changed • Description text on page 1 changed • Pin Descritption table rows changed: 8, 11, 12 • Sections changed: 3.9, 3.10, 3.15, 3.20, 3.21, 4.1, 4.2, 4.3, 4-7, 5.
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