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Features

• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors

• A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge

• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply

the Gate of the External Battery Reverse Protection NMOS

• 5V/3.3V Regulator and Current Limitation Function

• Reset Derived From 5V/3.3V Regulator Output Voltage

• Sleep Mode With Supply Current of Typically < 45 µA, Wake-up by Signal on Pins EN2

or on LIN Interface

• A Programmable Window Watchdog

• Battery Overvoltage Protection and Battery Undervoltage Management

• Overtemperature Warning and Protection (Shutdown)

• LIN 2.0 Compliant

• 3.3V/5V Regulator with Trimmed Band Gap

• QFN32 Package

1. Description

The ATA6823 is designed for several body and powertrain applications. The IC is

used to drive a continuous current motor in a full H-bridge configuration. An external

microcontroller controls the driving function of the IC by providing a PWM signal and a

direction signal and allows the use of the IC in a motor-control application. The PWM

control is performed by the low-side switch; the high-side switch is permanently on in

the driving phase. The VMODE configuration pin can be set to 5V or 3.3V mode (for

regulator and interface high level). The window watchdog has a programmable time,

programmable by choosing a certain value of the external watchdog resistor RWD,

internally trimmed to an accuracy of 10%. For communication a LIN transceiver 2.0 is

integrated.

H-bridge Motor

Driver

ATA6823

Preliminary

4856E–AUTO–07/07

Summary of content (28 pages)

PAGE 1
Features • PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors • A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge • Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply the Gate of the External Battery Reverse Protection NMOS • 5V/3.3V Regulator and Current Limitation Function • Reset Derived From 5V/3.
PAGE 2
Figure 1-1.
PAGE 3
ATA6823 [Preliminary] 2. Pin Configuration Pinning QFN32 EN2 VBATSW VBAT VCC PGND L1 L2 PBAT Figure 2-1. 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 Atmel YWW 21 ATA6823 20 ZZZZZ-AL 19 18 17 9 10 11 12 13 14 15 16 VG CPLO CPHI VRES H2 S2 H1 S1 TX DIR PWM EN1 RX DG3 DG2 DG1 VMODE VINT RWD CC /RESET WD GND LIN Note: Table 2-1.
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Table 2-1. Pin Description (Continued) Pin Symbol I/O Function 22 CPHI I 23 CPLO O 24 VG I/O 25 PBAT I Power supply (after reverse protection) for charge pump and H-bridge 26 L2 O Gate voltage H-bridge, low-side 2 27 L1 O Gate voltage H-bridge, low-side 1 28 PGND I Power ground for H-bridge and charge pump 29 VCC O 5V/100 mA supply for microcontroller, blocking capacitor 2.
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ATA6823 [Preliminary] 4. Application 4.1 General Remark This chapter describes the principal application for which the ATA6823 was designed. Because Atmel cannot be considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular purpose are given. Table 4-1. Typical External Components Component Function Value Tolerance CVINT Blocking capacitor at VINT 220 nF, 10V, X7R 10% CVCC Blocking capacitor at VCC 2.
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5.1.2 Voltage Supervisor This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it. Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out.
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ATA6823 [Preliminary] Pulling the EN2 pin up to the VBAT level will drive the IC into Active mode. EN2 is debounced with a time constant of 20 µs, based on a 100 kHz clock. • Go to Active using the LIN interface The second possibility for wake-up can be performed using the LIN transceiver. In Sleep mode, the LIN receiver is partially active. The wake-up by LIN requires 2 steps: 1.
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Figure 5-1. Wake-up by pin LIN LIN VBAT 55% VBAT VBAT - 1.
PAGE 9
ATA6823 [Preliminary] 5.4 5V/3.3V VCC Regulator The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 µF ceramic capacitor for stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V.
PAGE 10
After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The reset output, /RESET, stays low for the time tres (typically 68 ms), then switches to high. For an initial lead time td (typically 68 ms for setups in the controller) the watchdog waits for a rising edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the watchdog will reset the microcontroller for tres and wait td for the rising edge on WD.
PAGE 11
ATA6823 [Preliminary] 5.6.1 Transmit Mode During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus signal on pin LIN. To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave-shaping unit. Transmission will be interrupted in the following cases: • Thermal shutdown active or overtemperature LIN active • Sleep mode Figure 5-4.
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5.7 5.7.1 Control Inputs EN1, EN2, DIR, PWM Pins EN1, EN2 Any of the enable pins may be used to activate the IC with a HIGH. EN1 is a low level input, EN2 has to withstand a voltage up to 40V. Internal pull-down resistors are included. 5.7.2 Pin DIR Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is included. 5.7.3 Pin PWM Logical input for PWM information delivered by external microcontroller.
PAGE 13
ATA6823 [Preliminary] 5.8 VG Regulator The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage is reduced if the supply voltage at VBAT falls below 12V. 5.
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Figure 5-5. Timing of the Drivers PWM or DIR 50% t tLxHL tLxf tLxLH tLxr 80% tCC Lx 20% t tHxLH tCC tHxr tHxHL tHxf 80% Hx 20% t The delays tHxLH and tLxLH include the cross conduction time tCC. 5.12 Short Circuit Detection To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power NMOS.
PAGE 15
ATA6823 [Preliminary] 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PAGE 16
7. Thermal Resistance Parameters Symbol Value Unit Thermal resistance junction to heat slug Rthjc <5 K/W Thermal resistance junction to ambient when heat slug is soldered to PCB Rthja 25 K/W 8. Operating Range The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly.
PAGE 17
ATA6823 [Preliminary] 9. Electrical Characteristics All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max Unit Type* 1 Power Supply and Supervisor Functions 1.1 Current consumption VBAT VVBAT = 13.5V(1) 25, 30 IVBAT1 7 mA A 1.2 Current consumption VBAT VVBAT =13.5V in Standby mode 25, 30 IVBAT2 50 µA A 1.3 Internal power supply 2 VINT 4.8 4.94 5.1 V A 1.
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9. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise. No. Parameters 2.9 2.10 Test Conditions Pin Symbol HIGH threshold VMODE 1 VMODE H LOW threshold VMODE 1 VMODE L Min Typ Max Unit Type* 4.0 V A V A V A V A 0.7 3 Reset and Watchdog 3.1 VCC threshold voltage level for /RESET VMODE = “H” (VMODE = “L”) 29 VtHRESH 3.
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ATA6823 [Preliminary] 9. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise. No. Parameters Test Conditions 3.15 Open window (5) 3.16 Output low-voltage of /RESET At IOLRES = 1 mA 3.17 Internal pull-up resistor at pin /RESET 4 Pin Symbol Min Typ Max Unit 780 × TOSC t2 5 VOLRES 5 RPURES 5 10 Type* A 0.4 V A 15 kΩ D Lin Transceiver 4.
PAGE 20
9. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise. No. Parameters Pin Symbol Min 4.12 Leakage current at ground loss Control unit disconnected GNDDevice = VS from ground VBAT =12V Loss of local ground must 0V < VBUS < 18V not affect communication in the residual network 8 IBUS_NO_gnd –1 4.13 Node has to sustain the current that can flow VBAT disconnected under this condition.
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ATA6823 [Preliminary] 9. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise. No. Parameters 6.3 Period charge pump oscillator 6.4 CP load current in VG without CP load Load = 0A 6.5 CP load current in VG with CP load Load = 3 mA, CCP = 100 nF 7 Test Conditions Pin Symbol Min T100 9 Typ Max Unit Type* 11 µs A IVGCPz 100 µA D IVGCP 3.3 mA A H-bridge Driver 7.
PAGE 22
9. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise. No. Parameters Test Conditions 7.12 Static high-side switch output high-voltage pins H1, H2 ILx = –10 µA (PWM = static) 7.13 Sink resistance between Hx and ground in Sleep mode Pin Symbol Min VHxHstat1(7) Typ Max Unit VVBAT + VVG – 1 VVBAT + VVG V RHxsleep 3 10 kΩ VHxHdyn1 VVBAT + VVG – 1 VVBAT + VVG V tLxHL 0.5 µs tLxLH 0.
PAGE 23
ATA6823 [Preliminary] 9. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise. No. Parameters 7.27 Switching level of tCC comparator 7.28 Short circuit detection voltage 7.29 Short circuit detection time 8 Test Conditions Pin Symbol Min Typ Max Unit Vswtcc 0.653 × VVCC 0.667 × VVCC 0.68 × VVCC V (9) VSC 3.5 4 4.5 V (10) tSC 5 10 15 ms Input EN2 8.
PAGE 24
10. Schaffner and Electromagnetic Compatibility 10.1 Transients on Power-supply Rail (Battery) The application (including IC and external protection circuitry, see Figure 1-1 on page 2) has to withstand the test pulses in Table 10-1. Table 10-1. Test Pulses Test Pulse No. Test Level Duration or Number of Pulses Specs Acceptance level 1 –100V 10 min Ri = 10Ω A 2 150V 10 min Ri = 10Ω A 3a –200V 10 min Ri = 50Ω A 3b 200V 10 min Ri = 50Ω A A B 4 4V/5.5V 15 ms/2s Ri = 0.
PAGE 25
ATA6823 [Preliminary] Figure 10-3. Pulse 3a (Ri = 50Ω) 100 ns V 10 ms 90 ms 5 ns 12V 10% t 90% -200V 100 µs Figure 10-4. Pulse 3b (Ri = 50Ω) V 100 µs 200V 90% 10% 12V 10 ms t 90 ms 5 ns 100 ns Figure 10-5. Pulse 4 (Ri = 0.01Ω) 12V 5.5V 4.
PAGE 26
10.2 Transients on Pin LIN Transients to these pins are coupled capacitively to the IC and are valid for the application with external circuitry concerning figure 6. Values: Pulse 3a, Pulse 3b (see Figure 10-3 and Figure 10-4 on page 25) coupled via 1 nF to LIN, Ri = 50Ω Acceptance level A 10.
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ATA6823 [Preliminary] 12. Ordering Information Extended Type Number Package Remarks ATA6823-PHQY QFN32 Pb-free 13. Package Information Package: QFN 32 - 7 x 7 Exposed pad 4.7 x 4.7 Dimensions in mm Not indicated tolerances ± 0.05 7 0.9±0.1 4.7 +0 0.05-0.05 32 25 1 32 24 1 technical drawings according to DIN specifications 17 0.6 0.3 8 Drawing-No.: 6.543-5097.01-4 8 16 9 0.65 nom. 4.55 Issue: 1; 24.02.03 14.
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