Instruction Manual

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Features

• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors

• High Temperature Capability up to 200° C Junction

• A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge

• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply

the Gate of the External Battery Reverse Protection NMOS

• 5V/3.3V Regulator and Current Limitation Function

• Reset Derived From 5V/3.3V Regulator Output Voltage

• A Programmable Window Watchdog

• Battery Overvoltage Protection and Battery Undervoltage Management

• Overtemperature Warning and Protection (Shutdown)

• High Voltage Serial Interface for Communication

• QFN32 Package

1. Description

The ATA6824 is designed for high temperature mechatronic applications, for example

turbo chargers, where the electronic is mounted very close to the hot engine. In such

harsch environments the ICs have to withstand temperatures up to 150°C ambient

which results in junction temperatures up to 200°C. The IC is used to drive a continu-

ous current motor in a full H-bridge configuration. An external microcontroller controls

the driving function of the IC by providing a PWM signal and a direction signal and

allows the use of the IC in a motor-control application. The PWM control is performed

by the low-side switch; the high-side switch is permanently on in the driving phase.

The VMODE configuration pin can be set to 5V or 3.3V mode (for regulator and inter-

face high level). The window watchdog has a programmable time, programmable by

choosing a certain value of the external watchdog resistor RWD, internally trimmed to

an accuracy of 10%. To communicate with a host controller there is a HV Serial Inter-

face integrated.

High

Temperature

H-bridge Motor

Driver

ATA6824

Preliminary

4931C–AUTO–09/06

Summary of content (22 pages)

PAGE 1
Features • • • • • • • • • • • PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors High Temperature Capability up to 200° C Junction A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply the Gate of the External Battery Reverse Protection NMOS 5V/3.3V Regulator and Current Limitation Function Reset Derived From 5V/3.
PAGE 2
Figure 1-1.
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ATA6824 [Preliminary] 2. Pin Configuration Pinning QFN32 NC VBATSW VBAT VCC PGND L1 L2 PBAT Figure 2-1. 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 Atmel YWW 21 ATA6824 20 ZZZZZ-AL 19 18 17 9 10 11 12 13 14 15 16 VG CPLO CPHI VRES H2 S2 H1 S1 TX DIR PWM NC RX DG3 DG2 DG1 VMODE VINT RWD CC /RESET WD GND SIO Note: Table 2-1.
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Table 2-1. Pin Description (Continued) Pin Symbol I/O Function 22 CPHI I 23 CPLO O 24 VG I/O 25 PBAT I Power supply (after reverse protection) for charge pump and H-bridge 26 L2 O Gate voltage H-bridge, low-side 2 27 L1 O Gate voltage H-bridge, low-side 1 28 PGND I Power ground for H-bridge and charge pump 29 VCC O 5V/100 mA supply for microcontroller, blocking capacitor 2.
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ATA6824 [Preliminary] 4. Application 4.1 General Remark This chapter describes the principal application for which the ATA6824 was designed. Because Atmel cannot be considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular purpose are given. Table 4-1. Typical External Components Component Function Value Tolerance CVINT Blocking capacitor at VINT 220 nF, 10V, X7R 10% CVCC Blocking capacitor at VCC 2.
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5.1.2 Voltage Supervisor This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it. Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out.
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ATA6824 [Preliminary] Figure 5-1. Timing Diagram of the Watchdog Function tresshort tres /RESET td td t1 t2 t1 t2 WD 5.3.1 Timing Sequence For example, with an external resistor RWD = 33 kΩ ±1% we get the following typical parameters of the watchdog. TOSC = 12.32 µs, t1 = 12.1 ms, t2 = 9.61 ms, TWD = 16.88 ms ±10% The times tres = 68 ms and td = 68 ms are fixed values with a tolerance of 10%. After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on.
PAGE 8
If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms. The watchdog start sequence is similar to the power-on reset. The internal oscillator is trimmed to a tolerance of < ±10%. This means that t1 and t2 can also vary by ±10%. The following calculation shows the worst case calculation of the watchdog period Twd which the microcontroller has to provide. t1min = 0.90 × t1 = 10.87 ms, t1max = 1.10 × t1 = 13.28 ms t2min = 0.90 × t2 = 8.65ms, t2max = 1.10 × t2 = 10.
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ATA6824 [Preliminary] Figure 5-3.
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5.5 5.5.1 Control Inputs DIR and PWM Pin DIR Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is included. 5.5.2 Pin PWM Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed through to the H-bridge. An internal pull-down resistor is included. Table 5-1.
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ATA6824 [Preliminary] 5.6 VG Regulator The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage is reduced if the supply voltage at VBAT falls below 12V. 5.
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Figure 5-4. Timing of the Drivers PWM or DIR 50% t tLxHL tLxf tLxLH tLxr 80% tCC Lx 20% t tHxLH tCC tHxr tHxHL tHxf 80% Hx 20% t The delays tHxLH and tLxLH include the cross conduction time tCC. 5.10 Short Circuit Detection To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power NMOS.
PAGE 13
ATA6824 [Preliminary] 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PAGE 14
7. Thermal Resistance Parameters Symbol Value Unit Thermal resistance junction to heat slug Rthjc <5 K/W Thermal resistance junction to ambient when heat slug is soldered to PCB Rthja 25 K/W 8. Operating Range The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly.
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ATA6824 [Preliminary] 10. Electrical Characteristics All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max 1 Power Supply and Supervisor Functions 25, 30 IVBAT1 7 1.1 Current consumption VBAT VVBAT = 13.5V(1) 1.2 Internal power supply 2 VINT 4.8 4.94 5.1 1.235 1.3 Band gap voltage VBG Overvoltage threshold 1.4 30 VTHOV 19.8 22.3 VBAT Overvoltage threshold Measured during 1 1.5 30 VTOVhys 1.
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10. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max 3 Reset and Watchdog VMODE = “H” 4.9 VCC threshold voltage 29 VtHRESH 3.1 level for /RESET (VMODE = “L”) (3.25) Tracking of reset VMODE = “H” 100 3.1a thres-hold with regulated 29 VCC1-VtHRESH (VMODE = “L”) (70) output voltage VMODE = “H” 4.3 VCC threshold voltage 3.
PAGE 17
ATA6824 [Preliminary] 10. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max Internal pull-up resistor at 3.17 5 10 15 5 RPURES pin /RESET 4 High Voltage Serial Interface Normal mode; 4.1 Low-level output current 13 ILRX 4 VLIN = 0V, VRX = 0.4V Normal mode; 4.2 High-level output current VLIN = VBAT 13 IHRX 4 VRX = VCC – 0.4V 0.9 × Driver recessive output 4.
PAGE 18
10. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max Node has to sustain the current that can flow VBAT disconnected 4.13 under this condition. Bus VSUP_Device = GND 8 IBUS 100 must remain operational 0V < VBUS < 18V under this condition VBUS_CNT = Center of receiver 4.14 0.475 VS 0.5 VS 0.525 VS 8 VBUS_CNT (Vth_dom + Vth_rec)/2 threshold 4.
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ATA6824 [Preliminary] 10. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max Output peak current at ILxL, 100 7.4 pins L1, L2, switched to VLx = 3V x = 1, 2 LOW Output peak current at ILxH, 7.5 pins L1, L2, switched to VLx = 3V –100 x = 1, 2 HIGH Pull-down resistance at RPDLx 30 100 7.6 x = 1, 2 pins L1, L2 ON-resistance of sink RDSON_HxL, 20 7.
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10. Electrical Characteristics (Continued) All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max VVBAT = 13.5V 7.17 Fall time low-side driver 0.5 tLxf CGx=5 nF 7.18 Rise time low-side driver tLxr 0.5 Propagation delay time, Figure 5-4 on page 12 0.5 7.19 high-side driver from high tHxHL VVBAT = 13.5V to low Propagation delay time, 7.20 high-side driver from low tHxLH 0.5 + tCC to high VVBAT = 13.
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ATA6824 [Preliminary] 11. Ordering Information Extended Type Number ATA6824-PHQW Package Remarks QFN32 Pb-free 12.
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