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Features

• ATA6833 Temperature Range T

= 125°C, T

= 150°C

• ATA6834 Extended Temperature Range T

= 150°C, T

= 200°C

• Direct Driving of 6 External NMOS Transistors with a Maximum Switching Frequency of

50 kHz

• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply

the Gate of the External Battery Reverse Protection NMOS

• Built-in 5V/3.3V Voltage Regulator with Current Limitation

• Reset Signal for the Microcontroller

• Sleep Mode with Supply Current of typically < 45 µA

• Wake-up via LIN Bus or High Voltage Input

• Programmable Window Watchdog

• Battery Overvoltage Protection and Battery Undervoltage Management

• Overtemperature Warning and Protection (Shutdown)

• 200 mA Peak Current for Each Output Driver

• LIN Transceiver Conformal to LIN 2.1 and SAEJ2602-2 with Outstanding EMC and ESD

Performance

• QFN48 Package 7 mm × 7 mm

1. Description

The ATA6833 and ATA6834 are system basis chips for three-phase brushless DC

motor controllers designed in Atmel

’s state-of-the-art 0.8 µm SOI technology

SMART-I.S.

™

1. In combination with a microcontroller and six discrete power MOS-

FETs, the system basis chip forms a BLDC motor control unit for automotive

applications. In addition, the circuits provide a 3.3V/5V linear regulator and a window

watchdog.

The circuit includes various control and protection functions like overvoltage and over-

temperature protection, short circuit detection, and undervoltage management.

Thanks to these function blocks, the driver fulfils a maximum of safety requirements

and offers a high integration level to save cost and space in various applications. The

target applications are most suitable for the automotive market due to the robust tech-

nology and the high qualification level. ATA6834, in particular, is designed for

applications in a high-temperature environment.

BLDC Motor

Driver and LIN

System Basis

Chip

ATA6833

ATA6834

Preliminary

9122B–AUTO–10/08

Summary of content (25 pages)

PAGE 1
Features • ATA6833 Temperature Range TA = 125°C, TJ = 150°C • ATA6834 Extended Temperature Range TA = 150°C, TJ = 200°C • Direct Driving of 6 External NMOS Transistors with a Maximum Switching Frequency of 50 kHz • Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply the Gate of the External Battery Reverse Protection NMOS Built-in 5V/3.
PAGE 2
Figure 1-1. Block Diagram VBAT VBAT VBATSW VINT VG CPHI1 CPHI2 CPOUT CPLO1 CPLO2 PBAT VMODE DG1 DG2 Microcontroller DG3 3.
PAGE 3
ATA6833/ATA6834 [Preliminary] 2. Pin Configuration Pinning QFN48 VBATSW EN2 VBAT NC VCC PGND L3 L2 L1 VG PBAT NC Figure 2-1.
PAGE 4
Table 2-1.
PAGE 5
ATA6833/ATA6834 [Preliminary] 3. Functional Description 3.1 3.1.1 Power Supply Unit with Supervisor Functions Power Supply The IC has to be supplied by a reverse-protected battery voltage. To prevent damage to the IC, proper external protection circuitry has to be added. It is recommended to use at least one capacitor combination of storage and RF capacitors behind the reverse protection circuitry, which is connected close to the VBAT and GND pins of the IC.
PAGE 6
3.2 Active Mode and Sleep Mode The IC has two modes: Sleep Mode and Active Mode. Switching between the modes is described below. By default the IC starts in Active Mode (which means normal operation) after power-on. A Go to Sleep procedure switches the IC from Active Mode to Sleep Mode (standby). A Go to Active procedure brings the IC back from Sleep Mode to Active Mode.
PAGE 7
ATA6833/ATA6834 [Preliminary] 3.3 5V/3.3V VCC Regulator The 5V/3.3V regulator is fully integrated. It requires an external electrolytic capacitor in the range of 2.2 µF up to 10 µF and with an ESR in the range from 2Ω to 15Ω for stability (see Figure 3-2). The output voltage can be configured as either 5V or 3.3V by connecting pin VMODE to either pin VINT or GND. Since the regulator is not designed to be switched between both output voltages during operation, it is advisable to hard-wire VMODE pin.
PAGE 8
3.4 Reset and Watchdog Management The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time TOSC is determined by the external resistor RWD. A HIGH signal on WDD pin enables the watchdog function; a LOW signal disables it. Since WDD pin is equipped with an internal pull-up resistor the watchdog is enabled by default. In order to keep the current consumption as low as possible the watchdog is switched off during Sleep Mode.
PAGE 9
ATA6833/ATA6834 [Preliminary] Example: Using an external resistor RWD = 33 kΩ ±1% results in typical parameters as follows: TOSC = 12.32 µs t1 = 980 × TOSC = 12.07 ms ±10% t2 = 780 × TOSC = 9.609 ms ±10% t1 + t2 = 21.68 ms ±10% Hence, the minimum time the external microcontroller has to wait before pin WD can be triggered is in worst case tmin = 1.1 × t1 = 13.28 ms. The maximum time for the watchdog trigger on WD pin is t max = 0.9 × (t1 + t2) = 19.51 ms.
PAGE 10
3.6 VG Regulator The VG regulator provides a stable voltage to supply the low-side gate drivers and to deliver sufficient voltage for the external low-side Power-NMOS transistors. Typically the output voltage is 12V. In order to guarantee reliable operation even with a low battery voltage, the VG regulator is supplied by the charge pump output. For stability, an external ceramic capacitor of typically 470 nF has to be provided. There is no internal supervision of the VG output voltage. 3.
PAGE 11
ATA6833/ATA6834 [Preliminary] 3.8 Short Circuit Detection Short circuits in the motor bridge circuitry are sensed by S1 to S3 inputs. Internal comparators monitor the voltage differences between the drain and the source terminals of the external power-NMOS transistors. If one transistor switches on and the voltage drop from its drain to source stays higher than the threshold VSC (typical 4V) for a longer time than tSC (typically 6 µs), a short circuit in this branch is detected.
PAGE 12
3.10 Diagnostic Outputs D1 - D3 As mentioned in the sections above, the diagnostic outputs DG1 to DG3 are used to signal failures. This is summarized in the following table. Table 3-2.
PAGE 13
ATA6833/ATA6834 [Preliminary] Figure 3-7.
PAGE 14
4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to pin GND. [xxx] Values for the ATA6834.
PAGE 15
ATA6833/ATA6834 [Preliminary] 6. Operating Range The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly. [xxx] Values for the ATA6834 Parameters Symbol Min Max Unit 5.5 VTHOV(4) V VVBAT 4.3 5.
PAGE 16
8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. TJPW set 120 (170) 145 (195) 170 (220) °C B 1.12 Thermal prewarning reset TJPW reset 105 (155) 130 (180) 155 (205) °C B Thermal prewarning hysteresis ΔTJPW °C B 1.11 Thermal prewarning set 1.13 15 Unit Type* 1.
PAGE 17
ATA6833/ATA6834 [Preliminary] 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters Test Conditions 2.8 Output current limit VMODE = VINT, VBAT > 7V VMODE = GND, VBAT > 5.5V ILoad @ RESET, 150°C < TJ < 200°C Pin VCC Symbol IOS1 Min. 70 70 2.12 HIGH threshold VMODE VVMODE H 2.13 LOW threshold VMODE VVMODE L 0.
PAGE 18
8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters Test Conditions Pin Input leakage current Input leakage current at the driver off 4.10 receiver including pull-up VBUS = 0V resistor as specified VBAT = 12V Symbol Min.
PAGE 19
ATA6833/ATA6834 [Preliminary] 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters 4.22 5 Test Conditions Pin Dominant time for wake-up VLIN = 0V via LIN-bus Symbol Min. Typ. Max. Unit Type* TBUS 30 90 150 µs A 0.3 × VVCC V A V A Control Inputs EN1, IL1-3, IH1-3, WD, TX, WDD 5.1 Input low-level threshold VIL 5.
PAGE 20
8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters Test Conditions Pin Symbol Min. –100 8.4 Output peak current at pins VLx = 3V Lx switched to LOW ILxL 8.5 Output peak current at pins VLx = 3V Lx switched to HIGH ILxH 8.6 Sink resistance between Lx and GND 8.7 ON-resistance of sink stage VSx = 0V of pins Hx 8.
PAGE 21
ATA6833/ATA6834 [Preliminary] 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Propagation delay time, 8.21 high-side driver from high to low tHxHL 0.9 µs A Propagation delay time, 8.22 high-side driver from low to high tHxLH 0.9 µs A 8.
PAGE 22
9. Application This section describes the principal application for which the ATA6833/ATA6834 was designed. Figure 9-1. Typical Application Battery + CCPOUT PBAT CPOUT CPHI2 CPLO2 CCP2 CPHI1 CPLO1 CCP1 VG CVCC CVG VINT VBAT VBATSW CVINT VMODE VCC DG1 DG2 DG3 3.
PAGE 23
ATA6833/ATA6834 [Preliminary] Table 9-1. Component Typical External Components Min. Typical Max. CVINT Function Blocking capacitor at VINT 100 nF 220 nF/10V 470 nF CVCC Blocking capacitor at VCC 1.
PAGE 24
10. Ordering Information Extended Type Number Package ATA6833-PLQW QFN48 ATA6834-PLQW QFN48 Remarks 11. Package Information Package: VQFN_7 x 7_48L Exposed pad 4.5 x 4.5 Dimensions in mm Not indicated tolerances ±0.05 Bottom 4.5±0.15 Top 37 48 48 1 36 1 12 25 12 Pin 1 identification 24 7 Z 0.2 0.4±0.1 technical drawings according to DIN specifications Drawing-No.: 6.543-5137.01-4 Issue: 1; 19.10.06 0.5 nom. 5.5 0.9±0.1 Z 10:1 13 0.23±0.07 12.
PAGE 25
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