Manual

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Features

• Operates between 2.7V to 5.5V

• High-density, High-performance Electrically-erasable Complex

Programmable Logic Device

– 44-pin, 32 I/O CPLD

– 100% connected

– 12 ns Maximum Pin-to-pin Delay

– Registered Operation up to 90.9 MHz

– Fully Connected Input and Feedback Logic Array

• Flexible Logic Macrocell

– D/T/Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

• Advanced Power Management Features

– Pin-controlled 5 µA Standby Mode (Typical)

– Programmable Pin-keeper Inputs and I/Os

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-lead PLCC and TQFP Packages

• Advanced EEPROM Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latchup Immunity

• Supported by Popular Third-party Tools

• Security Fuse Feature

Description

The ATF1500ABV is a high-performance, high-density complex PLD. Built on an

advanced EEPROM technology, it has maximum pin-to-pin delays of 12 ns and sup-

ports sequential logic operation at speeds up to 90.9 MHz. With 32 logic macrocells

and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic

PLDs.

High-

performance

EE PLD

ATF1500ABV

Rev. 0723I–08/01

TQFP

Top View

I/O

GND

I/O

VCC

I/O

VCC

I/O

GND

I/O

GND

VCC

I/O

I/O/PD

VCC

OE2/I

GCLR/I

OE1/I

CLK/I

GND

I/O

PLCC

Top View

I/O

GND

I/O

VCC

I/O

VCC

I/O

GND

I/O

GND

VCC

I/O

I/O/PD

VCC

OE2/I

GCLR/I

OE1/I

CLK/I

GND

I/O

Pin Configurations

Name Function

CLK Clock

I Logic Inputs

I/O Bi-directional

Buffers

GCLR Register Reset

(active low)

OE1,

OE2

Output Enable

(active low)

VCC (+3V to 5.25V)

Supply

PD Power-down

(active high)

Summary of content (15 pages)

PAGE 1
Features • Operates between 2.7V to 5.5V • High-density, High-performance Electrically-erasable Complex Programmable Logic Device – 44-pin, 32 I/O CPLD – 100% connected – 12 ns Maximum Pin-to-pin Delay – Registered Operation up to 90.
PAGE 2
Functional Logic Diagram(1) Note: 2 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
PAGE 3
ATF1500ABV The ATF1500ABV’s 100% connected global input and feedback architecture simplifies logic placement and eliminates pinout changes due to design changes. Any Macrocell may be connected to any I/O pin. The ATF1500ABV has 32 bi-directional I/O pins and four dedicated input pins. Each dedicated input pin can also serve as a global control signal: register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.
PAGE 4
Input Diagram VCC INPUT 100K ESD PROTECTION CIRCUIT PROGRAMMABLE OPTION I/O Diagram VCC OE DATA I/O VCC 100K PROGRAMMABLE OPTION Design Software Support 4 ATF1500ABV designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats.
PAGE 5
ATF1500ABV ATF1500ABV Macrocell ATF1500ABV Macrocell The ATF1500ABV macrocell is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array inputs. Product Terms and Select Mux Each ATF1500ABV macrocell has five product terms.
PAGE 6
Flip-flop The ATF1500ABV’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate or from a separate product term. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low.
PAGE 7
ATF1500ABV Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .......................................-2.0V to +5.25V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.
PAGE 8
AC Waveforms Register AC Characteristics, Input Pin Clock(1) -12 Symbol 2.7-volt Adder Min Max Min Max Units Clock to Output .5 2 7 2 8 ns tCFS Clock to Feedback 0 3 3 ns tSIS I, I/O Setup Time 1 10 11 ns tSFS Feedback Setup Time 1 10 11 ns tHS Input, I/O, Feedback Hold Time 0 0 0 ns tPS Clock Period 1 13 14 ns tWS Clock Width .5 6.5 7 ns fMAXS External Feedback 1/(tSIS + tCOS) -5 58.8 52.6 MHz Internal Feedback 1/(tSFS + tCFS) -5.5 76.9 71.
PAGE 9
ATF1500ABV Register AC Characteristics, Product Term Clock(1) -12 Symbol Parameter tCOA (2) Clock to Output 2 tCFA Clock to Feedback 1 tSIA I, I/O Setup Time 0 4 4 ns tSFA Feedback Setup Time 0 4 4 ns tHA Input, I/O, Feedback Hold Time 0 4 4 ns tPA Clock Period 1 12 14 ns tWA Clock Width .5 6 7 ns fMAXA External Feedback 1/(tSIA + tCOA) -7 62.5 52.6 MHz Internal Feedback 1/(tSFA + tCFA) -6.4 83.3 71.4 MHz No Feedback 1/(tPA) -6.4 83.3 71.
PAGE 10
Power-down AC Characteristics(1) -12 Symbol Parameter tIVDH Valid I, I/O before PD High tGVDH (3) -15 2.
PAGE 11
ATF1500ABV Power-up Reset The ATF1500ABV’s registers are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be low on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1.
PAGE 12
Output Slew Rate Control Each ATF1500ABV macrocell contains a configuration bit for each I/O to control its output slew rate. This allows selected data paths to operate at maximum throughput while reducing system noise from outputs that are not speed-critical. Outputs default to slow edges, and may be individually set to fast in the design file. Output transition times for outputs configured as “slow” have a tSSO delay adder.
PAGE 13
ATF1500ABV Ordering Information tPD (ns) tCOS (ns) FMAXS (MHz) 12 6 15 8 Ordering Code Package Operation Range 62.5 ATF1500ABV-12AC ATF1500ABV-12JC 44A 44J Commercial (0°C to 70°C) 52.
PAGE 14
Packaging Information 44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) .045(1.14) X 45° 12.21(0.478) SQ 11.75(0.458) PIN 1 ID PIN NO. 1 IDENTIFY .045(1.14) X 30° - 45° .012(.305) .008(.203) .630(16.0) .590(15.0) .656(16.7) SQ .650(16.5) 0.45(0.018) 0.30(0.012) 0.80(0.031) BSC .032(.813) .026(.660) .695(17.7) SQ .685(17.4) .050(1.27) TYP .
PAGE 15
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