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Features

• High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 64 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44, 68, 84, 100 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

– D/T/Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

– Automatic µA Standby for “L” Version

– Pin-controlled 1 mA Standby Mode

– Programmable Pin-keeper Circuits on Inputs and I/Os

– Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP

• Advanced EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• 3.3V or 5.0V I/O Pins

• Security Fuse Feature

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• Transparent – Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

High-

performance

Complex

Programmable

Logic Device

ATF1504AS

ATF1504ASL

Rev. 0950N–PLD–07/02

Summary of content (33 pages)

PAGE 1
Features • High-density, High-performance, Electrically-erasable Complex Programmable • • • • • • • • • • Logic Device – 64 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 44, 68, 84, 100 Pins – 7.
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44-lead PLCC Top View I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 39 38 37 36 35 34 33 32 31 30 29 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT GCLK2/OE2/I I/GCLR I/OE1 GCLK1/I GND GCLK3/I/O I/O I/O VCCIO 1/O I/O I/O 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O VCCIO I/O/TDI I/O I/O I/O I/O GND I/O/PD1 I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68
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ATF1504AS(L) 100-lead TQFP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O NC NC I/O 100-lead PQFP Top View NC NC VCCIO I/O/TDI NC I/O NC I/O I/O I/O GN
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Description The ATF1504AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.
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ATF1504AS(L) Block Diagram I/O (MC64)/GCLK3 Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. The ATF1504AS device is an in-system programmable (ISP) device.
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Product Terms and Select Mux Each ATF1504AS macrocell has five product terms. Each product term receives as its possible inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.
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ATF1504AS(L) Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The sixteen foldback terms in each region allow generation of high fan-in sum terms (up to sixteen product terms) with a nominal additional delay. Figure 1.
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Programmable Pinkeeper Option for Inputs and I/Os The ATF1504AS offers the option of programming all input and I/O pins so that pinkeeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise.
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ATF1504AS(L) All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. All power-down AC characteristic parameters are computed from external input or I/O pins, with Reduced Power Bit turned on.
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Programming ATF1504AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF1504AS via the PC. ISP is performed by using either a download cable or a comparable board tester or a simple microprocessor interface.
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ATF1504AS(L) DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C VCCINT or VCCIO (5V) Power Supply 5V ± 5% 5V ± 10% 3.0V - 3.6V 3.0V - 3.6V VCCIO (3.
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Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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ATF1504AS(L) AC Characteristics (Continued) -7 Max Max Max Maximum Clock Frequency tIN Input Pad and Buffer Delay 0.5 0.5 2 2 2 ns tIO I/O Input Pad and Buffer Delay 0.5 0.5 2 2 2 ns tFIN Fast Input Delay 1 1 2 2 2 ns tSEXP Foldback Term Delay 4 5 8 10 12 ns tPEXP Cascade Logic Delay 0.8 0.8 1 1 1.
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AC Characteristics (Continued) -7 Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF) 4.0 5.0 7 tZX2 Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) 4.5 5.5 tZX3 Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 5.0V/3.
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ATF1504AS(L) Output AC Test Loads Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary). Power-down Mode The ATF1504AS includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 10 mA. During power-down, all output data and internal logic states are latched internally and held.
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JTAG-BST/ISP Overview The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1504AS. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary scan testing.
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ATF1504AS(L) BSC Configuration for Macrocell Pin BSC TDO 0 1 Pin DQ Capture DR Clock TDI Shift TDO OEJ 0 0 1 D Q D Q 1 OUTJ 0 0 Pin 1 D Q D Q Capture DR Update DR 1 Mode TDI Shift Clock Macrocell BSC 17 0950N–PLD–07/02
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PCI Compliance The ATF1504AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required by the PCI interface.
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ATF1504AS(L) PCI DC Characteristics Symbol Parameter VCC Conditions Min Max Units Supply Voltage 4.75 5.25 V VIH Input High Voltage 2.0 VCC + 0.5 V VIL Input Low Voltage -0.5 0.8 V IIH Input High Leakage Current VIN = 2.7V 70 µA IIL Input Low Leakage Current VIN = 0.5V -70 µA VOH Output High Voltage IOUT = -2 mA VOL Output Low Voltage IOUT = 3 mA, 6 mA CIN 2.4 V 0.
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ATF1504AS Dedicated Pinouts 44-lead TQFP 44-lead J-lead 68-lead J-lead 84-lead J-lead 100-lead PQFP 100-lead TQFP INPUT/OE2/GCLK2 40 2 2 2 92 90 INPUT/GCLR 39 1 1 1 91 89 INPUT/OE1 38 44 68 84 90 88 INPUT/GCLK1 37 43 67 83 89 87 I/O /GCLK3 35 41 65 81 87 85 I/O/PD (1,2) 5, 19 11, 25 17, 37 20, 46 14, 44 12, 42 I/O/TDI (JTAG) 1 7 12 14 6 4 I/O/TMS (JTAG) 7 13 19 23 17 15 I/O/TCK (JTAG) 26 32 50 62 64 62 I/O/TDO (JTAG) 32 38 57 71 75 7
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ATF1504AS(L) ATF1504AS I/O Pinouts 44- 44- 68- 84- 100- 100- 44- 44- 68- 84- 100- 100- lead lead lead lead lead lead lead lead lead lead lead lead MC PLC PLCC TQFP PLCC PLCC PQFP TQFP MC PLC PLCC TQFP PLCC PLCC PQFP TQFP 1 A 12 6 18 22 16 14 33 C 24 18 36 44 42 40 2 A – – – 21 15 13 34 C – – – 45 43 41 3 A/ PD1 11 5 17 20 14 12 35 C/ PD2 25 19 37 46 44 42 4 A 9 3 15 18 12 10 36 C 26 20 39 48 46 44 5 A 8
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SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE (TA = 25°C, F = 0) SUPPLY CURRENT VS. SUPPLY VOLTAGE (T A = 25°C, F = 0) 125 1100 100 1000 ICC (µA) ICC (mA) STANDARD 75 50 800 REDUCED POWER MODE 25 STANDARD POWER 900 REDUCED POWER MODE 700 0 4.50 4.75 5.00 5.25 4.50 5.50 4.75 5.00 5.25 5.50 V CC (V) V CC (V) SUPPLY CURRENT VS. FREQUENCY LOW-POWER ("L") VERSION LOW POWER (TA = 25°C) SUPPLY CURRENT VS. SUPPLY VOLTAGE LOW-POWER ("L") VERSION (TA = 25°C, F = 0) 125.
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ATF1504AS(L) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C) NORMALIZED TPD VS. TEMPERATURE (VCC = 5.0V) 43 1.2 42 41 NORMALIZED TPD IOL (mA) 40 39 38 37 36 35 1.1 1.0 0.9 34 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (C) NORMALIZED TPD VS. SUPPLY VOLTAGE (TA = 25°C) NORMALIZED TCO VS. SUPPLY VOLTAGE (TA = 25°C) 1.10 1.2 1.00 NORMALIZED TPD NORMALIZED TPD 1.20 0.90 0.80 4.5 4.8 5.0 5.3 5.5 1.1 1.0 0.
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NORMALIZED TCO VS.TEMPERATURE (V CC = 5.0V) NORMALIZED TCO 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (C) NORMALIZED TSU VS. TEMPERATURE (VCC = 5.0V) NORMALIZED TSU 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 75.
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ATF1504AS(L) ATF1504AS Ordering Information tPD (ns) tCO1 (ns) fMAX (MHz) 7.5 4.5 166.
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ATF1504ASL Ordering Information tPD (ns) tCO1 (ns) fMAX (MHz) 20 12 25 15 Ordering Code Package Operation Range 83.
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ATF1504AS(L) Packaging Information 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.
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44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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ATF1504AS(L) 68J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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84J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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ATF1504AS(L) 100Q1 – PQFP Dimensions in Millimeters and (Inches)* *Controlling dimensions: millimeters JEDEC STANDARD MS-022, GC-1 17.45 (0.687) 16.95 (0.667) PIN 1 ID PIN 1 20.10 (0.791) 19.90 (0.783) 0.65 (0.0256) BSC 0.40 (0.016) 23.45 (0.923) 0.22 (0.009) 22.95 (0.904) 14.12 (0.556) 13.90 (0.547) 0.23 (0.009) 0.11 (0.004) 3.40 (0.134) MAX 0º~7º 1.03 (0.041) 0.73 (0.029) 0.50 (0.020) 0.25 (0.010) 04/11/2001 R DRAWING NO. TITLE 2325 Orchard Parkway 100Q1, 100-lead, 14 x 20 mm Body, 3.
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100A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.
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