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Features

• High-density, High-performance, Electrically-erasable Complex

Programmable Logic Device

– 3.0 to 3.6V Operating Range

– 64 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44, 68, 84, 100 Pins

– 15nsMaximumPin-to-pinDelay

– Registered Operation up to 77 MHz

– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

– D/T/Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open-collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

– Automatic 5 µA Standby for “L” Version

– Pin-controlled 100 µA Standby Mode (Typical)

– Programmable Pin-keeper Circuits on Inputs and I/Os

– Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP

• Advanced EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• Security Fuse Feature

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• Transparent-latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Low-voltage,

Complex

Programmable

Logic Device

ATF1504ASV

ATF1504ASVL

Rev. 1409H–PLD–09/02

Summary of content (29 pages)

PAGE 1
Features • High-density, High-performance, Electrically-erasable Complex • • • • • • • • • Programmable Logic Device – 3.0 to 3.
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44-lead PLCC Top View I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 39 38 37 36 35 34 33 32 31 30 29 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O 84-lead PLCC Top View 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O VCCIO I/O/TDI I/O I/O I/O I/O GND I/O/PD1 I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O I/O GND I/O/TDO I/O I/O I/O I/O VCCIO I/O
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ATF1504ASV(L) 100-lead TQFP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O NC NC I/O 100-lead PQFP Top View NC NC VCCIO I/O/TDI NC I/O NC I/O I/O I/O G
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Description The ATF1504ASV(L) is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.
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ATF1504ASV(L) Block Diagram Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. The ATF1504ASV(L) device is an in-system programmable (ISP) device.
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OR/XOR/CASCADE Logic The ATF1504ASV(L)’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term.
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ATF1504ASV(L) Figure 1. ATF1504ASV(L) Macrocell Programmable Pin-keeper Option for Inputs and I/Os The ATF1504ASV(L) offers the option of programming all input and I/O pins so that pin keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise.
PAGE 8
Input Diagram I/O Diagram Speed/Power Management The ATF1504ASV(L) has several built-in speed and power management features. The ATF1504ASV(L) contains circuitry that automatically puts the device into a low power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power savings for most applications running at system speeds below 5 MHz. This feature may be selected as a device option.
PAGE 9
ATF1504ASV(L) All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. The ATF1504ASV(L) macrocell also has an option whereby the power can be reduced on a per macrocell basis.
PAGE 10
Programming ATF1504ASV(L) devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. A t m e l p r o v i d e s I S P h a r d w a r e a n d s o f t w a r e t o a l lo w p r o g r a m m in g o f t h e ATF1504ASV(L) via the PC. ISP is performed by using either a download cable, a comparable board tester or a simple microprocessor interface.
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ATF1504ASV(L) DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient)) 0°C - 70°C -40°C - 85°C VCC (3.3V) Power Supply 3.0V - 3.6V 3.0V - 3.6V DC Characteristics Symbol Parameter Condition IIL Input or I/O Low Leakage Current VIN = V CC IIH Input or I/O High Leakage Current IOZ Tri-State Output Off-State Current Min VO = VCC or GND Typ Max Units -2 -10 µA 2 10 -40 40 µA Com. 60 mA Ind. 75 mA Com. 5 µA Ind.
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Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PAGE 13
ATF1504ASV(L) AC Characteristics -15 Symbol Parameter tPD1 -20 Min Max Min Max Units Input or Feedback to Non-Registered Output 3 15 20 ns tPD2 I/O Input or Feedback to Non-Registered Feedback 3 12 16 ns tSU Global Clock Setup Time 11 13.5 ns tH Global Clock Hold Time 0 0 ns tFSU Global Clock Setup Time of Fast Input 3 3 ns tFH Global Clock Hold Time of Fast Input 1.
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AC Characteristics (Continued) -15 Symbol Parameter Max Units tZX2 Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) 7 9 ns tZX3 Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF) 10 11 ns tXZ Output Buffer Disable Delay (CL = 5 pF) 6 7 ns tSU Register Setup Time 5 6 ns tH Register Hold Time 4 5 ns tFSU Register Setup Time of Fast Input 2 2 ns tFH Register Hold Time of Fast Input 2 2 ns tRD Register Delay 2 2.
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ATF1504ASV(L) Power-down Mode The ATF1504ASV(L) includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 3 mA. During power down, all output data and internal logic states are latched internally and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a High-Z state at the onset will remain at High-Z.
PAGE 16
JTAG-BST/ISP Overview The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1504ASV(L). The boundary-scan technique involves the inclusion of a shiftregister stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing.
PAGE 17
ATF1504ASV(L) BSC Configuration for Macrocell Pin BSC TDO 0 1 Pin DQ Capture DR Clock TDI Shift TDO OEJ 0 0 1 D Q D Q 1 OUTJ 0 0 Pin 1 D Q D Q Capture DR Update DR 1 Mode TDI Shift Clock Macrocell BSC 17 1409H–PLD–09/02
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ATF1504ASV Dedicated Pinouts 44-lead TQFP 44-lead J-lead 68-lead J-lead 84-lead J-lead 100-lead PQFP 100-lead TQFP INPUT/OE2/GCLK2 40 2 2 2 92 90 INPUT/GCLR 39 1 1 1 91 89 INPUT/OE1 38 44 68 84 90 88 INPUT/GCLK1 37 43 67 83 89 87 I/O /GCLK3 35 41 65 81 87 85 5, 19 11, 25 17, 37 20, 46 14, 44 12, 42 I/O / TDI (JTAG) 1 7 12 14 6 4 I/O / TMS (JTAG) 7 13 19 23 17 15 I/O / TCK (JTAG) 26 32 50 62 64 62 I/O / TDO (JTAG) 32 38 57 71 75 73 GN
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ATF1504ASV(L) ATF1504ASV I/O Pinouts 44-lead 44-lead 68-lead 84-lead PLCC TQFP PLCC PLCC 100lead PQFP 100lead TQFP 44-lead 44-lead 68-lead 84-lead PLCC TQFP PLCC PLCC 100lead PQFP 100lead TQFP MC PLC MC PLC 1 A 12 6 18 22 16 14 33 C 24 18 36 44 42 40 2 A - - - 21 15 13 34 C - - - 45 43 41 3 A/ PD1 11 5 17 20 14 12 35 C/ PD2 25 19 37 46 44 42 4 A 9 3 15 18 12 10 36 C 26 20 39 48 46 44 5 A 8 2 14 17 11 9 37 C 27 21 40 49 4
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SUPPLY CURRENT VS. FREQUENCY LOW-POWER ("L") VERSION (T A = 25°C) SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25°C, F = 0) 100 100.0 75 80.0 STANDARD POWER ICC (mA) ICC (mA) STANDARD POWER 50 REDUCED POWER MODE 60.0 40.0 REDUCED POWER 25 20.0 0 2.50 2.75 3.00 3.25 3.50 3.75 0.0 0.00 4.00 5.00 SUPPLY VOLTAGE (V) 10.00 15.00 20.00 FREQUENCY (MHz ) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C) SUPPLY CURRENT VS.
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ATF1504ASV(L) INPUT CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 100 15 80 10 INPUT CURRENT (uA) IOL (mA) OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, T A = 25°C) 60 40 20 0 5 0 -5 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) INPUT CURRENT (mA) 0 -20 -40 -60 -80 -100 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.
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ATF1504ASV(L) Ordering Information tPD (ns) tCO1 (ns) fMAX (MHz) 15 8 15 Ordering Code Package Operation Range 100 ATF1504ASV-15 AC44 ATF1504ASV-15 JC44 ATF1504ASV-15 JC68 ATF1504ASV-15 JC84 ATF1504ASV-15 QC100 ATF1500ASV-15 AC100 44A 44J 68J 84J 100Q1 100A Commercial (0°C to 70°C) 8 100 ATF1504ASV-15 AI44 ATF1504ASV-15 JI44 ATF1504ASV-15 JI68 ATF1504ASV-15 JI84 ATF1504ASV-15 QI100 ATF1504ASV-15 AI100 44A 44J 68J 84J 100Q1 100A Industrial (-40°C to +85°C) 20 12 83.
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ATF1504ASV(L) Packaging Information 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.
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44J – PLCC 1.14(0.045) X 45° PIN NO. 1 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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ATF1504ASV(L) 68J – PLCC 1.14(0.045) X 45° PIN NO. 1 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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84J – PLCC 1.14(0.045) X 45° PIN NO. 1 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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ATF1504ASV(L) 100Q1 – PQFP Dimensions in Millimeters and (Inches)* *Controlling dimensions: millimeters JEDEC STANDARD MS-022, GC-1 17.45 (0.687) 16.95 (0.667) PIN 1 ID PIN 1 20.10 (0.791) 19.90 (0.783) 0.65 (0.0256) BSC 0.40 (0.016) 23.45 (0.923) 0.22 (0.009) 22.95 (0.904) 14.12 (0.556) 13.90 (0.547) 0.23 (0.009) 0.11 (0.004) 3.40 (0.134) MAX 0º~7º 1.03 (0.041) 0.73 (0.029) 0.50 (0.020) 0.25 (0.010) 04/11/2001 R DRAWING NO. TITLE 2325 Orchard Parkway 100Q1, 100-lead, 14 x 20 mm Body, 3.
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100A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.
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