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Features

• High-density, High-performance, Electrically-erasable Complex

Programmable Logic Device

– 128 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 84, 100, 160 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

• Flexible Logic Macrocell

– D/T/Latch Configured Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register within a COM Output

• Advanced Power Management Features

– Automatic 10 µA Standby for “L” Version

– Pin-controlled 1 mA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages

• Advanced EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• Fast In-System Programmability (ISP) via JTAG

• PCI-compliant

• 3.3 or 5.0V I/O Pins

• Security Fuse Feature

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• Transparent-latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts

High-

performance

EE PLD

ATF1508AS

ATF1508ASL

Rev. 0784O–PLD–09/02

Summary of content (30 pages)

PAGE 1
Features • High-density, High-performance, Electrically-erasable Complex • • • • • • • • • • Programmable Logic Device – 128 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 84, 100, 160 Pins – 7.
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100-lead PQFP Top View 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/O I/O I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O/TDO I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O 80
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ATF1508AS(L) Block Diagram 8 to 12 16 3 0784O–PLD–09/02
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Description The ATF1508AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count and increase odds of successful pin-locked design modifications.
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ATF1508AS(L) Flip-flop The ATF1508AS’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flowthrough latch.
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Figure 1. ATF1508AS Macrocell Programmable Pin-keeper Option for Inputs and I/Os The ATF1508AS offers the option of programming all input and I/O pins so that “pin-keeper” circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise.
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ATF1508AS(L) Speed/Power Management The ATF1508AS has several built-in speed and power management features. The ATF1508AS contains circuitry that automatically puts the device into a low-power stand-by mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power-savings for most applications running at system speeds below 5 MHz. To further reduce power, each ATF1508AS macrocell has a Reduced-power bit feature.
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Design Software Support ATF1508AS designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats. Power-up Reset The ATF1508AS is designed with a power-up reset, a feature critical for state machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will depend on the polarity of its buffer.
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ATF1508AS(L) ISP Programming Protection The ATF1508AS has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper option preserves the former state during device programming. All ATF1508AS devices are initially shipped in the erased state thereby making them ready to use for ISP.
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BSC Configuration Pins and Macrocells (Except JTAG TAP Pins) Note: The ATF1508AS has a pull-up option on TMS and TDI pins. This feature is selected as a design option. BSC Configuration for Macrocell TDO OEJ 0 0 1 D Q D Q 1 OUTJ 0 0 Pin 1 D Q D Q Capture DR Update DR 1 Mode TDI Shift Clock Macrocell BSC Boundary Scan Definition Language (BSDL) Models for the ATF1508 10 These are now available in all package types via the Atmel Web Site.
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ATF1508AS(L) PCI Voltage-tocurrent Curves for +5V Signaling in Pull-up Mode The ATF1508AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. Pull Up VCC Test Point Voltage PCI Compliance 2.4 DC drive point 1.
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PCI DC Characteristics Symbol Parameter Conditions Min Max Units VCC Supply Voltage 4.75 5.25 V VIH Input High Voltage 2.0 VCC + 0.5 V VIL Input Low Voltage -0.5 0.8 V VIN = 2.7V 70 µA VIN = 0.5V -70 µA IIH Input High Leakage Current (1) (1) IIL Input Low Leakage Current VOH Output High Voltage IOUT = -2 mA VOL Output Low Voltage IOUT = 3 mA, 6 mA CIN 2.4 V 0.
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ATF1508AS(L) Power-down Mode The ATF1508AS includes two pins for optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high, the device supply current is reduced to less than 10 mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at highZ.
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DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C VCCINT or VCCIO (5V) Power Supply 5V ± 5% 5V ± 10% 2.7V - 3.6V 2.7V - 3.6V VCCIO (3.
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ATF1508AS(L) Pin Capacitance(1) Typ Max Units Conditions CIN 8 10 pF VIN = 0V; f = 1.0 MHz CI/O 8 10 pF VOUT = 0V; f = 1.0 MHz Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. Timing Model U Input Test Waveforms and Measurement Levels rR, tF = 1.5 ns typical Output AC Test Loads (3.
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SUPPLY CURRENT VS. FREQUENCY LOW-POWER ("L") VERSION (TA = 25°C) SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25°C, F = 0) 200.0 250.0 STANDARD POWER 150.0 STANDARD POWER ICC (mA) ICC (mA) 200.0 150.0 REDUCED POWER MODE 100.0 REDUCED POWER MODE 50.0 100.0 0.0 50.0 4.50 4.75 5.00 V CC (V) 5.25 0.00 5.50 5.00 10.00 FREQUENCY (MHz) 15.00 20.00 OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, T A = 25°C) SUPPLY CURRENT VS. SUPPLY VOLTAGE LOW-POWER ("L") VERSION (TA = 25°C, F = 0) 0 30.
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ATF1508AS(L) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VCC = 5V, TA = 25°C) NORMALIZED TCO VS. SUPPLY VOLTAGE (TA = 25°C) 1.20 -10 NORMALIZED TPD IOH (mA) -30 -50 -70 1.10 1.00 0.90 -90 -110 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.80 4.50 5.0 4.75 5.00 SUPPLY VOLTAGE (V) OUTPUT VOLTAGE (V) INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5V, TA = 25°C) 5.25 5.50 NORMALIZED TSU VS. SUPPLY VOLTAGE (T A = 25°C) 40 1.20 1.10 20 NORMALIZED TSU INPUT CURRENT ( µ A) 30 10 0 -10 1.
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NORMALIZED TSU VS. TEMPERATURE (VCC = 5.0V) NORMALIZED TSU 1.20 1.10 1.00 0.90 0.
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ATF1508AS(L) AC Characteristics (1) -7 Min -10 Max Min -15 -20 Max Min Max 7.5 10 3 15 7 9 3 12 Symbol Parameter tPD1 Input or Feedback to Non-registered Output tPD2 I/O Input or Feedback to Non-registered Feedback tSU Global Clock Setup Time 6 7 11 16 20 ns tH Global Clock Hold Time 0 0 0 0 0 ns tFSU Global Clock Setup Time of Fast Input 3 3 3 3 3 ns tFH Global Clock Hold Time of Fast Input 0.5 0.5 1.0 1.
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AC Characteristics (Continued)(1) -7 Symbol Parameter Min tOD2 Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) tOD3 Output Buffer and Pad Delay (Slow slew rate = ON; VCCIO = 5V or 3.3V; C L = 35 pF) tZX1 -10 Max Min -15 Max Min -20 Max Min -25 Max Min Max Units 2.5 2.0 5 6 7 ns 5 5.5 8 10 12 ns Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF) 4.0 5.
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ATF1508AS(L) ATF1508AS Dedicated Pinouts Dedicated Pin 84-lead J-lead 100-lead PQFP 100-lead TQFP 160-lead PQFP INPUT/OE2/GCLK2 2 92 90 142 INPUT/GCLR 1 91 89 141 INPUT/OE1 84 90 88 140 INPUT/GCLK1 83 89 87 139 I/O /GCLK3 81 87 85 137 12,45 3,43 1,41 63,159 I/O / TDI(JTAG) 14 6 4 9 I/O / TMS(JTAG) 23 17 15 22 I/O / TCK(JTAG) 62 64 62 99 I/O / TDO(JTAG) 71 75 73 112 7,19,32,42, 47,59,72,82 13,28,40,45, 61,76,88,97 11,26,38,43, 59,74,86,95 17,42,60,66,9
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ATF1508AS I/O Pinouts MC PLB 84-lead J-lead 100-lead PQFP 100-lead TQFP 160-lead PQFP MC PLB 84-lead J-lead 100-lead PQFP 100-lead TQFP 160-lead PQFP 1 A – 4 2 160 33 C – 27 25 41 2 A – – – – 34 C – – – – 3 A/ PD1 12 3 1 159 35 C 31 26 24 33 4 A – – – 158 36 C – – – 32 5 A 11 2 100 153 37 C 30 25 23 31 6 A 10 1 99 152 38 C 29 24 22 30 7 A – – – – 39 C – – – – 8 A 9 100 98 151 40 C 28 23 21 29 9 A –
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ATF1508AS(L) ATF1508AS I/O Pinouts (Continued) MC PLB 84-lead J-lead 100-lead PQFP 100-lead TQFP 160-lead PQFP MC PLB 84-lead J-lead 100-lead PQFP 100-lead TQFP 160-lead PQFP 66 E – – – – 98 G – – – – 67 E/ PD2 45 43 41 63 99 G 64 66 64 101 68 E – – – 64 100 G – – – 102 69 E 46 44 42 65 101 G 65 67 65 103 70 E – 46 44 67 102 G – 69 67 105 71 E – – – – 103 G – – – – 72 E 48 47 45 68 104 G 67 70 68 106 73 E 49 4
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ATF1508AS Ordering Information tPD (ns) tCO1 (ns) fMAX (MHz) 7.5 4.5 166.
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ATF1508AS(L) ATF1508ASL Ordering Information tPD (ns) tCO1 (ns) fMAX (MHz) 20 12 25 25 Ordering Code Package 83.
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Package Information 84J – PLCC 1.14(0.045) X 45° PIN NO. 1 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
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ATF1508AS(L) 100Q1 – PQFP E PIN 1 ID PIN 1 e D1 B D E1 COMMON DIMENSIONS (Unit of Measure = mm) JEDEC STANDARD MS-022, GC-1 A 0º~7º C L A1 SYMBOL MIN NOM MAX A – 3.04 3.4 A1 0.25 0.33 0.5 D 23.20 BSC E 17.20 BSC E1 B 14.00 BSC 0.22 D1 L e NOTE – 0.40 20 BSC 0.73 – 1.03 0.65 BSC 09/10/2002 R DRAWING NO. TITLE 2325 Orchard Parkway 100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch, 100Q1 San Jose, CA 95131 Plastic Quad Flat Package (PQFP) REV.
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100A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.
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ATF1508AS(L) 160Q1 – PQFP D1 D E E1 Top View Bottom View A2 A1 e b COMMON DIMENSIONS (Unit of Measure = mm) L1 SYMBOL Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation DD-1, for additional information. 2. To be determined at seating plane. 3.
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