User guide

1
Features
High-density, High-performance, Electrically-erasable
Complex Programmable Logic Device
3.0V to 3.6V Operating Range
128 Macrocells
5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
84, 100, 160 Pins
15nsMaximumPin-to-pinDelay
Registered Operation up to 77 MHz
Enhanced Routing Resources
Flexible Logic Macrocell
D/T/Latch Configurable Flip-flops
Global and Individual Register Control Signals
Global and Individual Output Enable
Programmable Output Slew Rate
Programmable Output Open Collector Option
Maximum Logic Utilization by Burying a Register within a COM Output
Advanced Power Management Features
Automatic 5 µA Standby for “L Version
Pin-controlled 100 µA Standby Mode
Programmable Pin-keeper Inputs and I/Os
Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 84-lead PLCC and 100-lead PQFP and TQFP and
160-lead PQFP Packages
Advanced EE Technology
100% Tested
Completely Reprogrammable
10,000 Program/Erase Cycles
20 Year Data Retention
2000V ESD Protection
200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
Edge-controlled Power-down “L
Individual Macrocell Power Option
Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
High-
performance
EE PLD
ATF1508ASV
ATF1508ASVL
Rev. 1408F–PLD–10/02

Summary of content (23 pages)