User Manual

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High-

performance

EE-based CPLD

ATF1516AS

ATF1516ASL

Preliminary

Features

• High-density, High-performance, Electrically-erasable Complex

Programmable Logic Device

– 256 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 160, 192, 208 pins

– 10 ns Maximum Pin-to-pin Delay

– Registered Operation Up To 100 MHz

– Enhanced Routing Resources

• Flexible Logic Macrocell

– D/T/Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register within a COM Output

• Advanced Power Management Features

– Automatic 3 mA Standby for “L” Version (Maximum)

– Pin-controlled 4 mA Standby Mode (Typical)

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 160-lead PQFP, 192-pin PGA, and 208-lead RQFP Packages

• Advanced EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• Fast In-System Programmability (ISP) via JTAG

• PCI-compliant

• 3.3 or 5.0V I/O Pins

• Security Fuse Feature

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• D-latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Edge Controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Rev. 0994D–09/99

Summary of content (13 pages)

PAGE 1
Features • High-density, High-performance, Electrically-erasable Complex • • • • • • • • • • Programmable Logic Device – 256 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 160, 192, 208 pins – 10 ns Maximum Pin-to-pin Delay – Registered Operation Up To 100 MHz – Enhanced Routing Resources Flexible Logic Macrocell – D/T/Latch Configurable Flip-flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Pr
PAGE 2
Block Diagram 6 to 12 P O N M E L F K G J H I 256 2 ATF1516AS(L)
PAGE 3
ATF1516AS(L) Description The ATF1516AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 256 logic macrocells and up to 164 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1516AS’s enhanced routing switch matrices increase usable gate count and increase odds of successful pin-locked design modifications.
PAGE 4
Product Terms and Select MUX Each ATF1516AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.
PAGE 5
ATF1516AS(L) Programmable Pin-keeper Option for Inputs and I/Os The ATF1516AS offers the option of programming all input and I/O pins so that “pin keeper” circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise.
PAGE 6
process users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large option by including the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the following condition is added: 4. If VCC falls below 2.0V, it must shut off completely before the device is turned on again.
PAGE 7
ATF1516AS(L) Input Test Waveforms and Measurement Levels Output AC Test Loads: (3.0V)* (703 )* (8060 )* rR, tF = 1.5 ns typical Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary). Power-down Mode The ATF1516AS includes two pins for optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high, the device supply current is reduced to less than 3 mA.
PAGE 8
JTAG-BST Overview The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1516AS. The boundary-scan technique involves the inclusion of a shiftregister stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundaryscan cell (BSC) in order to support boundary-scan testing.
PAGE 9
ATF1516AS(L) BSC Configuration for Macrocell Pin BSC TDO 0 1 Pin DQ Capture DR Clock TDI Shift TDO OEJ 0 0 1 D Q D Q 1 OUTJ 0 0 Pin 1 D Q D Q Capture DR Update DR 1 Mode TDI Shift Clock Macrocell BSC 9
PAGE 10
PCI Compliance The ATF1516AS also supports the growing need in the industry to support the new peripheral component interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. PCI Voltage-to-current Curves for +5V Signaling in Pull-up Mode Pull Up VCC Voltage Test Point 2.4 DC drive point 1.
PAGE 11
ATF1516AS(L) Ordering Information tPD (ns) tCO1 (ns) fMAX (MHz) 10 5 15 Ordering Code Package Operation Range 125 ATF1516AS-10QC160 ATF1516AS-10UC192 ATF1516AS-10QHC208 160Q 192U 208QH Commercial (0°C to 70°C) 8 100 ATF1516AS-15QC160 ATF1516AS-15UC192 ATF1516AS-15QHC208 160Q 192U 208QH Commercial (0°C to 70°C) 15 8 100 ATF1516AS-15Q160 ATF1516AS-15UI192 ATF1516AS-15QHI208 160Q 192U 208QH Industrial (-40°C to +85°C) 20 12 83.
PAGE 12
Packaging Information 160Q, 160-lead, Plastic Quad FlatPack (PQFP) 1.238(31.45) SQ 1.218(30.95) PIN 1 ID .016(0.40) .008(0.20) .0256(0.65) BSC 1.106(28.10) .009(0.23) 7 0 1.098(27.90) SQ .157(3.97) .127(3.22) .004(0.10) .037(0.95) .025(0.65) 12 .020(0.50) .002(0.
PAGE 13
Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd.