Manual

Features
16 Channel GPS Correlator
8192 Search Bins with GPS Acquisition Accelerator
Accuracy: 2.5m CEP (Stand-Alone, S/A off)
Time to First Fix: 34s (Cold Start)
Acquisition Sensitivity: –140 dBm
Tracking Sensitivity: –150 dBm
Utilizes the ARM7TDMI
®
ARM
®
Thumb
®
Processor Core
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Embedded ICE (In-circuit Emulator)
128 Kbyte Internal RAM
384 Kbyte Internal ROM with u-blox GPS Firmware
Fully Programmable External Bus Interface (EBI)
Maximum External Address Space of 8 Mbytes
Up to 4 Chip Selects
Software Programmable 8-bit/16-bit External Data Bus
6-channel Peripheral Data Controller (PDC)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
2 External Interrupts
32 User-programmable I/O Lines
1 USB Device Port
Universal Serial Bus (USB) V2.0 Full-speed Device Specification Compliant
Embedded USB V2.0 Full-speed Transceiver
Suspend/Resume Logic
Ping-pong Mode for Isochronous and Bulk Endpoints
2 USARTs
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Master/Slave SPI Interface
2 Dedicated Peripheral Data Controller (PDC) Channels
8-bit to 16-bit Programmable Data Length
4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
Peripherals Can Be Deactivated Individually
Geared Master Clock to Reduce Power Consumption
Sleep State with Disabled Master Clock
Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
2.3V to 3.6V or 1.8V Supply Voltage
Includes Power Supervisor
1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
1 Kbyte Battery Backup Memory
9 mm × 9 mm 100-pin BGA Package (LFBGA100)
Electrostatic sensitive device.
Observe precautions for handling.
GPS Baseband
Processor
ATR0621
Summary
Preliminary
Rev. 4890AS–GPS–09/05
Note: This is a summary document. A complete document
is available under NDA. For more information, please con-
tact your local Atmel sales office.

Summary of content (20 pages)