Manual

ManualsBrandsRainbow Electronics ManualsGPS receiverATR0625

Features

• 16-channel GPS Correlator

– 8192 Search Bins with GPS Acquisition Accelerator

– Accuracy: 2.5m CEP (Stand-Alone, S/A off)

– Time to First Fix: 34s (Cold Start)

– Acquisition Sensitivity: –142 dBm

– Tracking Sensitivity: –158 dBm

• Utilizes the ARM7TDMI

ARM

Thumb

Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Embedded ICE (In-circuit Emulator)

• 128 Kbyte Internal RAM

• 384 Kbyte Internal ROM with u-blox GPS Firmware

• 6-channel Peripheral Data Controller (PDC)

• 8-level Priority, Individually Maskable, Vectored Interrupt Controller

– 2 External Interrupts

• 24 User-programmable I/O Lines

• 1 USB Device Port

– Universal Serial Bus (USB) V2.0 Full-speed Device

– Embedded USB V2.0 Full-speed Transceiver

– Suspend/Resume Logic

– Ping-pong Mode for Isochronous and Bulk Endpoints

• 2 USARTs

– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART

• Master/Slave SPI Interface

– 2 Dedicated Peripheral Data Controller (PDC) Channels

– 8-bit to 16-bit Programmable Data Length

– 4 External Slave Chip Selects

• Programmable Watchdog Timer

• Advanced Power Management Controller (APMC)

– Peripherals Can Be Deactivated Individually

– Geared Master Clock to Reduce Power Consumption

– Sleep State with Disabled Master Clock

– Hibernate State with 32.768 kHz Master Clock

• Real Time Clock (RTC)

• 2.3V to 3.6V or 1.8V Core Supply Voltage

• Includes Power Supervisor

• 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance

• 4 Kbytes Battery Backup Memory

• 8 mm × 8 mm 56 Pin QFN56 Package

• Pb-free, RoHS-compliant, Green

GPS Baseband

Processor

SuperSense

ATR0625

Preliminary

Rev. 4925A–GPS–02/06

Summary of content (26 pages)

PAGE 1
Features • 16-channel GPS Correlator • • • • • • • • • • • • • • • • • • – 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.
PAGE 2
1. Description The GPS baseband processor ATR0625 includes a 16-channel GPS correlator and is based on the ARM7TDMI® processor core. This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0625 has two USART and an USB device port. This port is compliant with the Universal Serial Bus (USB) V2.
PAGE 3
ATR0625 [Preliminary] Advanced Power Management Controller XT_IN XT_OUT GPS Correlators RTC NSHDN NSLEEP GPS Accelerator ATR0625 Block Diagram SRAM RF_ON CLK23 SMD Generator P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0 SIGLO0 SIGHI0 Timer Counter Figure 1-1.
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2. Architectural Overview 2.1 Description The ATR0625 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories. The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides an interface between the ASB and the APB.
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ATR0625 [Preliminary] 3. Pin Configuration 3.1 Pinout Figure 3-1. Pinout QFN56 (Top View) 42 29 43 28 ATR0625 56 15 1 Table 3-1.
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Table 3-1.
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ATR0625 [Preliminary] 3.2 Signal Description Table 3-2.
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Table 3-2. Module ATR0625 Signal Description (Continued) Name TMS JTAG/ICE Test Data In TCK 8 Internal pull-up resistor Internal pull-up resistor – – Test Clock Input – Test Reset Input Input Low Internal pull-down resistor Debug Enable Input High Internal pull-down resistor Clock Input Input – Interface to ATR0601, Schmitt trigger input Output – PIO-controlled after reset I/O Low VDD18 Power – Core voltage 1.8V VDDIO Power – Variable IO voltage 1.65V to 3.
PAGE 9
ATR0625 [Preliminary] 3.3 Setting GPSMODE0 to GPSMODE12 The start-up configuration of a ROM-based system without external non-volatile memory is defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0625 can be stored in an external non-volatile memory like EEPROM.
PAGE 10
3.3.2 Sensitivity Settings Table 3-5. GPSMODE3 (Fixed PU) 3.3.3 GPS Sensitivity Settings GPSMODE2 (Reset = PU) Description 0 0 Auto mode 0 1 Fast mode 1 0 Normal mode (Default ROM value) 1 1 High sensitivity Serial I/O Configuration The ATR0625 features a two-stage I/O message and protocol selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port.
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ATR0625 [Preliminary] The following message settings are used in the tables below: Table 3-7. NMEA Port UBX Port Table 3-8. NMEA Port UBX Port Table 3-9. NMEA Port UBX Port Table 3-10.
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3.3.4 USB Power Mode For correct response to the USB host queries, the device has to know its power mode. This is configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported to the USB host; that is, the device classifies itself as a “low-power bus-powered function” with no more than one USB power unit load. Table 3-12. USB Power Modes GPSMODE7 (Reset = PU) Description 3.3.5 0 USB device is bus-powered (max.
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ATR0625 [Preliminary] Table 3-14. Antenna Detection I/O Settings GPSMODE11 GPSMODE10 GPSMODE8 (Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET Comment 0 0 0 P25/NAADET0/MISO 0 0 1 P25/NAADET0/MISO 0 1 0 P14/NAADET1 0 1 1 P14/NAADET1 (Default ROM value) 1 0 0 P14/NAADET1 Reserved for further use. Do not use this setting. 1 0 1 P14/NAADET1 Reserved for further use. Do not use this setting. 1 1 0 P25/NAADET0/MISO 1 1 1 P25/NAADET0/MISO Reserved for further use.
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3.4 External Connections for a Working GPS System Figure 3-2.
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ATR0625 [Preliminary] Table 3-15. Recommended Pin Connection Pin Name Recommended External Circuit P0/NANTSHORT Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if configured as output by user application. P1/GPSMODE0 Internal pull-down resistor, leave open, in order to disable the GPSMODE pin configuration feature. Connect to VDDIO to enable the GPSMODE pin configuration feature.
PAGE 16
3.4.1 Connecting an Optional Serial EEPROM The ATR0625 offers the possibility to connect an external serial EEPROM. The internal ROM firmware supports to store the configuration of the ATR0625 in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected with the ATR0625. The 32-bit RISC processor of the ATR0625 accesses the external memory with SPI (Serial Peripheral Interface). Atmel recommend to use 32 Kbit 1.8V serial EEPROM, e.g. the Atmel AT25320AY1-1.8.
PAGE 17
ATR0625 [Preliminary] 4. Power Supply The baseband IC is supplied with four distinct supply voltages: • VDD18, the nominal 1.8V supply voltage for the core, the RF-I/O pins, the memory interface and the test pins and all GPIO-pins not mentioned in next item. • VDDIO, the variable supply voltage within 1.8V to 3.6V for following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 In input mode, these pins are 5V input tolerant.
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The baseband IC contains a built in low dropout voltage regulator LDO18. This regulator can be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case, LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and 3.6V. The LDO_EN input can be used to shut down VDD18 if the system is in standby mode. If the host system does however supply a 1.8V core voltage directly, this voltage has to be connected to the VDD18 supply pins of the baseband IC.
PAGE 19
ATR0625 [Preliminary] The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is enabled if VDD_USB within 3.0V and 3.6V. Figure 4-3. External Wiring Example Using Internal LDOs, USB Supply Voltage and Backup Power Supply ATR0625 internal LDO_IN NSHDN LDO_EN LDO_OUT LDO18 ldoin ldoen ldoout VDD18 Core VDDIO 1.8V to 3.3V variable IO Domain 1 µF (X7R) ldobat_in LDOBAT LDOBAT_IN 1.5V to 3.
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5. Oscillator Figure 5-1. Crystal Connection ATR0625 internal XT_IN 32 kHz Crystal Oscillator 32.768 kHz 50 ppm 32.768 kHz clock RTC XT_OUT max. 25 pF max. 25 pF 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.
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ATR0625 [Preliminary] 7. Electrical Characteristics If no additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C. No. Parameters 1.1 Pin Symbol Min. Typ. Max. Unit DC Supply Voltage Core VDD18 VDD18 1.65 1.8 1.95 V 1.2 DC Supply Voltage VDDIO Domain(1) VDDIO VDDIO 1.65 1.8/3.3 3.6 V 1.3 DC Supply Voltage USB(2) VDD_USB VDDUSB 3.0 3.3 3.6 V 1.4 DC Supply Voltage Backup Domain(3) VBAT18 VBAT18 1.65 1.8 3.
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7. Electrical Characteristics (Continued) If no additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C. No. Parameters Test Conditions 1.23 Input-leakage Current (standard Inputs and I/Os) VDD18 = 1.95V VIL = 0V Pin 1.24 Input Capacitance Symbol Min. ILEAK –1 Typ. ICAP Max. Unit +1 µA 10 pF 1.25 Input Pull-up Resistor NRESET RPU 0.7 1.6 kΩ 1.26 Input Pull-up Resistor TCK, TDI, TMS RPU 10 30 kΩ 1.
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ATR0625 [Preliminary] 8. Power Consumption Mode Conditions Typ. Unit (1) Sleep At 1.8V, no CLK23 0.065 Shutdown RTC, backup SRAM and LDOBAT 0.007(1) Normal Note: Satellite acquisition 25 Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA 14 All channels disabled 11 mA 1. Specified value only 9. ESD Sensitivity The ATR0625 is an ESD sensitive device. The current ESD values are to be defined. Observe precautions for handling 10.
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11. LDOBAT and Backup Domain The LDOBAT is a built in low dropout voltage regulator which provides the supply voltage VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. Table 11-1. Electrical Characteristics of LDOBAT Parameter Conditions Supply voltage LDOBAT_IN Typ. 2.3 Supply voltage VBAT 1.5 Output Voltage (VBAT18) If switch connects to LDOBAT_IN. 1.65 Output Current (VBAT18) 1.8 Max.
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ATR0625 [Preliminary] 12. Ordering Information Extended Type Number Package MPQ Remarks ATR0625-PYQW QFN56 2000 8 mm × 8 mm, 0.50 mm pitch, Pb-free, RoHS-compliant, green ATR0625-EK1 - 1 Evaluation kit/Road test kit ATR0625-DK1 - 1 Development kit inclusive example design information 13. Package QFN56 Package: QFN56 8 x 8 Exposed pad 6.5 x 6.5 Dimensions in mm Not indicated tolerances ±0.05 8 0.9 max. +0 6.5 0.05-0.
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