Manual

ManualsBrandsRainbow Electronics ManualsGPS receiverATR0630

Features

•

16-channel GPS Correlator

– 8192 Search Bins with GPS Acquisition Accelerator

– Accuracy: 2.5m CEP (2D, Stand Alone)

– Time to First Fix: 34s (Cold Start)

– Acquisition Sensitivity: –139 dBm (With External LNA)

– Tracking Sensitivity: –149 dBm (With External LNA)

•

Utilizes the ARM7TDMI

ARM

Thumb

Processor Core

– High-performance 32-bit RISC Architecture

– Embedded ICE (In-Circuit Emulation)

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128 Kbytes Internal RAM

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384 Kbytes Internal ROM with u-blox GPS Firmware

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1.5-bit ADC On-chip

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Single IF Architecture

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2 External Interrupts

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24 User-programmable I/O Lines

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1 USB Device Port

– Universal Serial Bus (USB) 2.0 Full-speed Device

– Embedded USB V2.0 Full-speed Transceiver

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2 USARTs

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Master/Slave SPI Interface

– 4 External Slave Chip Selects

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Programmable Watchdog Timer

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Advanced Power Management Controller (APMC)

– Geared Master Clock to Reduce Power Consumption

– Sleep State with Disabled Master Clock

– Hibernate State with 32.768 kHz Master Clock

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Real Time Clock (RTC)

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1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance

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4 KBytes of Battery Backup Memory

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7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant

Benefits

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Fully Integrated Design With Low BOM

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No External Flash Memory Required

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Requires Only a GPS XTAL, No TCXO

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Supports NMEA, UBX Binary and RTCM Protocol

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Supports SBAS (WAAS, EGNOS, MSAS)

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Up to 4Hz Update Rate

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Supports A-GPS (Aiding)

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Excellent Noise Performance

ANTARIS4

Single-chip

GPS Receiver

ATR0630

Preliminary

Rev. 4920A–GPS–01/06

Summary of content (35 pages)

PAGE 1
Features • 16-channel GPS Correlator • • • • • • • • • • • • • • • • – 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.
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1. Description The ATR0630 is a low-power, single-chip GPS receiver, especially designed to meet the requirements of mobile applications. It is based on Atmel’s ANTARIS™4 technology and integrates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm 96 pin BGA package. Providing excellent RF performance with low noise figure and low power consumption.
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ATR0630 [Preliminary] 2. Architectural Overview 2.1 Block Diagram Figure 2-1.
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2.2 General Description The ATR0630 has been designed especially for mobile applications. It provides high isolation between GPS and cellular bands, as well as very low power consumption. ATR0630 is based on the successful ANTARIS4 technology which includes the ANTARIS ROM software, developed by u-blox AG, Switzerland.
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ATR0630 [Preliminary] 2.7 VGA/AGC The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally load the input of the following analog-to-digital converter. The AGC control loop can be selected for on-chip closed-loop operation or for baseband controlled gain mode. 2.8 Analog-to-digital Converter The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced comparators and a sub-sampling unit, clocked by the reference frequency (fXTO).
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3. Pin Configuration 3.1 Pinout Figure 3-1. Pinning BGA96 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F ATR0630 G H Table 3-1.
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ATR0630 [Preliminary] Table 3-1.
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Table 3-1.
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ATR0630 [Preliminary] Table 3-1. Pin Name VDD_USB ATR0630 Pinout (Continued) BGA 96 (3) Pin Type A10 Supply VDD18 H9 Supply VDD18 G11 Supply VDD18 F12 Supply VDD18 B9 Supply VDD18 E5 Supply B5 Supply VDDIO H5 Supply VDIG A5 Supply X A2 Analog OUT XT_IN A12 Analog IN XT_OUT B12 Analog OUT XTO A1 Analog Input (4) VDDIO Notes: Pull Resistor (Reset Value)(1) PIO Bank A Firmware Label I O 1.
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Table 3-2.
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ATR0630 [Preliminary] Table 3-2.
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3.3 Setting GPSMODE0 to GPSMODE12 The start-up configuration of this ROM-based system without external non-volatile memory is defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0630 can be stored in an external non-volatile memory like EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 = 0).
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ATR0630 [Preliminary] 3.3.2 Sensitivity Settings Table 3-5. GPSMODE3 (Fixed PU) 3.4 GPS Sensitivity Settings GPSMODE2 (Reset = PU) Description 0 0 Auto mode 0 1 Fast mode 1 0 Normal mode (Default ROM value) 1 1 High sensitivity Serial I/O Configuration The ATR0630 features a two-stage I/O-message and protocol-selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port.
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The following message settings are used in the tables below: Table 3-7. NMEA Port UBX Port Table 3-8. NMEA Port UBX Port Table 3-9. NMEA Port UBX Port Table 3-10.
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ATR0630 [Preliminary] 3.4.1 USB Power Mode For correct response to the USB host queries, the device has to know its power mode. This is configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported to the USB host; that is, the device classifies itself as a “low-power bus-powered function” with no more than one USB power unit load. Table 3-12. USB Power Modes GPSMODE7 (Reset = PU) Description 3.4.
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Table 3-14. Antenna Detection I/O Settings GPSMODE11 GPSMODE10 GPSMODE8 (Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET Comment 0 0 0 P25/NAADET0/MISO 0 0 1 P25/NAADET0/MISO 0 1 0 P14/NAADET1 0 1 1 P14/NAADET1 (Default ROM value) 1 0 0 P14/NAADET1 Reserved for further use. Do not use this setting. 1 0 1 P14/NAADET1 Reserved for further use. Do not use this setting. 1 1 0 P25/NAADET0/MISO 1 1 1 P25/NAADET0/MISO Reserved for further use. Do not use this setting.
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ATR0630 [Preliminary] 3.4.3 External Connections for a Working GPS System Figure 3-2. Example of an External Connection (ATR0630) ATR0630 LNA (optional) SAW NC NC NC SIGHI SIGLO CLK23 RF NRF ATR0610 RF_ON PURF NSLEEP PUXTO NC NC NC NC NC NC NC see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 NRESET TMS TCK TDI NTRST TDO DBG_EN P0 - 2 P9 P12 - 17 P19 P23 - 27 P29 - 30 P30/AGCOUT0 SDI NC NC GND analog MO TEST EGC XT_IN 32.
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Table 3-15. Recommended Pin Connections Pin Name Recommended External Circuit P0/NANTSHORT Internal pull-down resistor; leave open if Antenna Supervision functionality is unused. Can be left open if configured as output by user application. P1/GPSMODE0 Internal pull-down resistor; leave open in order to disable the GPSMODE pin configuration feature. Connect to VDDIO to enable the GPSMODE pin configuration feature. Refer to GPSMODE definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
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ATR0630 [Preliminary] 3.5 Connecting an Optional Serial EEPROM The ATR0630 offers the possibility of connecting an external serial EEPROM. The internal ROM firmware supports storing the configuration of the ATR0630 in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected to the ATR0630. The ATR0630’s 32-bit RISC processor accesses the external memory via SPI (serial peripheral interface). For best results, use a 32-Kbit 1.8V serial EEPROM such as Atmel’s AT25320AY1-1.8.
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4. Power Supply The ATR0630 is supplied with six distinct supply voltages: • The power supplies for the RF part (VCC1, VCC2, VBP) within 2.7V to 3.3V. • VDIG, the 1.8V supply of the digital pins of the RF part (SIGHI, SIGLO and CLK23). VDIG should be connected to VDD18. • VDD18, the nominal 1.8V supply voltage for the core, the I/O pins, the memory interface and the test pins and all GPIO pins not mentioned in next item. • VDDIO, the variable supply voltage within 1.8V to 3.
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ATR0630 [Preliminary] Figure 4-1. Connecting Example: Separate Power Supplies for RF and Digital Part Using the Internal LDOs ATR0630 internal VCC1 2.7V to 3.3V VCC2 RF VBP VDIG 2.3V to 3.6V LDO_IN NSHDN LDO_EN LDO_OUT LDO18 ldoin ldoen ldoout VDD18 Core VDDIO 1.8V to 3.3V variable I/O domain 1 µF (X7R) ldobat_in LDOBAT LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 vbat vbat18 VDD 1 µF (X7R) RTC backup memory 0V or 3V to 3.
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The RTC section will be initialized properly if VDD18 is supplied first to the ATR0630. If VBAT is applied first, the current consumption of the RTC and backup SRAM is undetermined. Figure 4-2. Connecting Example: Common Power Supplies for RF and Digital Part Using the Internal LDOs ATR0630 internal VCC1 VCC2 RF VBP VDIG 2.7V to 3.3V LDO_IN NSHDN LDO_EN LDO_OUT LDO18 ldoin ldoen ldoout VDD18 Core VDDIO 1.8V to 3.3V variable IO domain 1 µF (X7R) ldobat_in LDOBAT LDOBAT_IN 1.5V to 3.
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ATR0630 [Preliminary] Figure 4-3. Connecting Example: Separate Power Supplies for RF and Digital Part Using 1.8V from Host System ATR0630 internal VCC1 2.7V to 3.3V VCC2 RF VBP VDIG LDO_IN LDO_EN LDO_OUT LDO18 ldoin ldoen ldoout 1.65V to 1.95V VDD18 Core VDDIO 1.8V to 3.3V variable I/O domain 1 µF (X7R) ldobat_in 2.3V to 3.6V LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 LDOBAT vbat vbat18 VDD 1 µF (X7R) RTC backup memory 0V or 3V to 3.
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Figure 4-4. Connecting Example: Power Supply from USB Using the Internal LDOs ATR0630 internal VCC1 VCC2 RF VBP VDIG LDO_IN NSHDN LDO_EN LDO_OUT LDO18 ldoin ldoen ldoout VDD18 Core VDDIO 1.8V to 3.3V variable I/O domain 1 µF (X7R) ldobat_in LDOBAT LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 vbat vbat18 VDD 1 µF (X7R) RTC backup memory USB-VSB 5V 24 External LDO 2.7V to 3.
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ATR0630 [Preliminary] 5. Crystals The ATR0630 only needs a GPS crystal (XTAL), but supports also TCXOs. The reference frequency is 23.104 MHz. By connecting an optional RTC crystal, different power modes are available. The reference frequency is 32.768 kHz. 5.1 GPS XTAL Figure 5-1. Application Example Using a GPS Crystal with ESR Typically = 12Ω (See Table 5-1 on page 27) A1 B3 XTO NXTO 47 pF A2 27 X 82 pF B2 NX X1 47 pF Figure 5-2.
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Figure 5-3. Equivalent Application Examples Using a GPS TCXO (See Table 5-3 on page 27) 33 pF A1 XTO 10 pF B3 TCXO 22 pF NXTO A2 Do not connect X B2 NX A1 10 pF XTO 33 pF B3 TCXO 22 pF A2 Do not connect NXTO X B2 NX Figure 5-4.
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ATR0630 [Preliminary] Table 5-1. Specification of GPS Crystals Appropriate for the Application Example Shown in Figure 5-1 on page 25 Parameter Comment Min Typ Max Units Frequency Characteristics Fundamental frequency Nominal frequency referenced to 25°C Calibration tolerance Frequency at 23°C ±2°C Frequency deviation Over operating temperature range Temperature range Operating temperature range 23.104 MHz 7.0 ±ppm 15.0 ±ppm –40.0 +85.0 °C 18.5 19.
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5.2 RTC Oscillator Figure 5-5. Crystal Connection ATR0630 internal XT_IN 32 kHz Crystal Oscillator 32.768 kHz 50 ppm 32.
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ATR0630 [Preliminary] 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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8. Operating Range Parameters Analog supply voltage RF Pins Symbol Min VCC1, VCC2, VBP VCC 2.70 Typ Max Unit 3.30 V Digital supply voltage RF VDIG VDIG 1.65 1.8 1.95 V Digital supply voltage core VDD18 VDD18 1.65 1.8 1.95 V Digital supply voltage VDDIO domain(1) VDDIO VDDIO 1.65 1.8/3.3 3.6 V Digital supply voltage USB(2) VDD_USB VDD_USB 3.0 3.3 3.6 V DC supply voltage LDO18 DC supply voltage LDOBAT DC Supply voltage VBAT LDO_IN LDO_IN 2.3 3.
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ATR0630 [Preliminary] 9. Electrical Characteristics (Continued) If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C. No. Parameters Test Conditions Pin Symbol 2.4 AGC cut-off frequency Cext = open A4 f3dB_AGC 250 kHz 2.5 AGC cut-off frequency Cext = 100 pF A4 f3dB_AGC 33 kHz 2.6 Gain-control output voltage A4 VAGCO 3 Min Typ Max 0.9 2.3 Unit V Reference Oscillator 3.
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9. Electrical Characteristics (Continued) If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C. No. Parameters Test Conditions 7.5 Low-level input voltage VDDIO domain 7.6 Symbol Min Max Unit VDDIO = 1.65V to 3.6V VIL,IO –0.3 +0.41 V High-level input voltage VDDIO domain VDDIO = 1.65V to 3.6V VIH,IO 1.46 5.0 V 7.7 Low-level input voltage VBAT18 domain VBAT18 = 1.65V to 1.95V A11, B10, C10, D10 VIL,BAT –0.3 +0.
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ATR0630 [Preliminary] 9. Electrical Characteristics (Continued) If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C. No. Parameters 7.24 Pin Symbol Min Max Unit Input pull-down resistors –40°C to +85°C DBG_EN, NTRST, RF_ON E8, H11 RPD 7 18 kΩ 7.25 Input pull-down resistors P0, P15, P30 F10, C8, F11, G12 RPD 100 235 kΩ 7.
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11. Ordering Information Extended Type Number Package MPQ Remarks ATR0630-7KQY BGA96 2000 7 mm × 10 mm, 0.8 mm pitch, Pb-free, RoHS-compliant ATR0630-EK1 - 1 Evaluation kit/Road test kit 1 Design kit including design guide and PCB Gerber files ATR0630-DK1 - 12. Package Information Package: ATR0630 Dimensions in mm n 0.08 m n 0.15 m 2. C BA 0.4±0.05 A1 Corner Top View Bottom View A1 Corner A B C D E F G H 0.8 7±0.05 0.8 Pin A1 Laser Marking A 8.8 10±0.
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