Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 1K Byte In-System Programmable Flash Program Memory Endurance: 1,000 Write/Erase Cycles – 64 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program Data Security Peripheral Features – Interrup
Description The ATtiny15L is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny15L achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers.
ATtiny15L Block Diagram Figure 1.
Pin Descriptions VCC Supply voltage pin. GND Ground pin. Port B (PB5..PB0) Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). PB5 is input or open-drain output. The use of pin PB5 is defined by a fuse and the special function associated with this pin is External Reset. The port pins are tristated when a reset condition becomes active, even if the clock is not running. Port B also accommodates analog I/O pins.
ATtiny15L ATtiny15L Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single-clock-cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Two of the 32 registers can be used as a 16-bit pointer for indirect memory access.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All the different interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
ATtiny15L The Program and Data Addressing Modes The ATtiny15L AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the various addressing modes supported in the ATtiny15L. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. Register Direct, Singleregister Rd Figure 4. Direct Single-register Addressing The operand is contained in register d (Rd).
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 7. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. “n” is the destination or source register address. Relative Program Addressing, RJMP and RCALL Figure 8. Relative Program Memory Addressing +1 Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. Constant Addressing using the LPM Instruction Figure 9.
ATtiny15L Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), and LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). Subroutine and Interrupt Hardware Stack The ATtiny15L uses a 3-level-deep Hardware Stack for subroutines and interrupts. The Hardware Stack is nine bits wide and stores the Program Counter (PC) return address while subroutines and interrupts are executed.
Figure 11. Single Cycle ALU Operation T1 T2 T3 T4 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back I/O Memory The I/O space definition of the ATtiny15L is shown in Table 2. Table 2.
ATtiny15L Table 2. ATtiny15L I/O Space(1) (Continued) Address Hex Note: Name Function $06 ADCSR ADC Control and Status Register $05 ADCH ADC Data Register High $04 ADCL ADC Data Register Low 1. Reserved and unused locations are not shown in the table. All ATtiny15L I/O and peripheral registers are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space.
• Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set description for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set description for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation.
ATtiny15L The most typical and general program setup for the Reset and Interrupt Vector Addresses are: Address Labels Code Comments $000 rjmp RESET ; Reset handler $001 rjmp EXT_INT0 ; IRQ0 handler $002 rjmp PIN_CHANGE ; Pin change handler $003 rjmp TIM1_CMP ; Timer1 compare match $004 rjmp TIM1_OVF ; Timer1 overflow handler $005 rjmp TIM0_OVF ; Timer0 overflow handler $006 rjmp EE_RDY ; EEPROM Ready handler $007 rjmp ANA_COMP ; Analog Comparator handler $008 rjmp ADC
Figure 12. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit BODEN BODLEVEL Brown-out Reset Circuit Reset Circuit Watchdog Timer Watchdog Oscillator Tunable Internal Oscillator Delay Counters CK TIMEOUT CKSEL[1:0] Table 4. Reset Characteristics (VCC = 5.0V)(1) Symbol Parameter Condition Min Typ Max Units Power-on Reset Threshold Voltage (rising) BOD disabled 1.0 1.4 1.8 V BOD enabled 1.7 2.2 2.
ATtiny15L Table 5. Reset Delay Selections(1) BODEN (2) CKSEL [1:0](2) Start-up Time, tTOUT at VCC = 2.7V Start-up Time, tTOUT at VCC = 5.0V x 00 256 ms + 18 CK 64 ms + 18 CK BOD disabled, slowly rising power x 01 256 ms + 18 CK 64 ms + 18 CK BOD disabled, slowly rising power x 10 16 ms + 18 CK 4 ms + 18 CK BOD disabled, quickly rising power 1 11 18 CK + 32 µs 18 CK + 8 µs BOD disabled 0 11 18 CK + 128 µs 18 CK + 32 µs BOD enabled Notes: Recommended Usage 1.
Figure 13. “MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 14. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET External Reset An External Reset is generated by a low-level on the RESET pin. Reset pulses longer than 500 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATtiny15L Brown-out Detection ATtiny15L has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and VCC decreases below the trigger level, the Brown-out Reset is immediately activated. When VCC increases above the trigger level, the Brown-out Reset is deactivated after a delay.
MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 $34 – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set (one) if a Watchdog Reset occurs.
ATtiny15L Interrupt Handling The ATtiny15L has two 8-bit Interrupt Mask Control Registers: GIMSK (General Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set the I-bit (one) to enable interrupts. The Ibit is set (one) when a Return from Interrupt instruction (RETI) is executed.
The corresponding interrupt of External Interrupt Request 0 is executed from Program memory address $001. See also “External Interrupts.” • Bit 5 – PCIE: Pin Change Interrupt Enable When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the interrupt on pin change is enabled. Any change on any input or I/O pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from Program memory address $002. See also “Pin Change Interrupt.
ATtiny15L vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR). • Bit 5..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 ( Ti me r / C o u n te r0 Ov e r f lo w In t e rr u p t En a b le ) a n d T OV 0 a re s e t ( o n e ) , t h e Timer/Counter0 Overflow interrupt is executed.
ATtiny15L • Bits 4, 3 – SM1, SM0: Sleep Mode Select Bits 1 and 0 These bits select between the three available sleep modes, as shown in Table 7. Table 7. Sleep Modes SM1 SM0 Sleep Mode 0 0 Idle mode 0 1 ADC Noise Reduction mode 1 0 Power-down mode 1 1 Reserved For details, refer to “Sleep Modes” below. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero.
ADC Noise Reduction Mode When the SM1/SM0 bits are “01”, the SLEEP instruction forces the MCU into the ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupt pin, pin change interrupt and the Watchdog (if enabled) to continue operating. Please note that the clock system including the PLL is also active in the ADC Noise Reduction mode. This improves the noise environment for the ADC, enabling higher resolution measurements.
ATtiny15L Timer/Counters The ATtiny15L provides two general purpose 8-bit Timer/Counters. The Timer/Counters h a ve s e p a ra te p r e s c a lin g s e l e c tio n f r o m s e p a ra te 1 0 - b i t p r e s c a le r s . T h e Timer/Counter0 uses internal clock (CK) as the clock time base. The Timer/Counter1 may use either the internal clock (CK) or the fast peripheral clock (PCK) as the clock time base. The Timer/Counter0 Prescaler Figure 18 shows the Timer/Counter prescaler. Figure 18.
The Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 $2C – – – – – FOC1A PSR1 PSR0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bit 2 – FOC1A: Force Output Compare 1A Writing a logical “1” to this bit forces a change in the Compare Match Output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0.
ATtiny15L CS00 CS01 CS02 TOV0 TOV0 TOV1 OCF1A TOIE0 TOIE1 OCIE1A Figure 20. Timer/Counter0 Block Diagram T/C CLK SOURCE The Timer/Counter0 Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 $33 – – – – – CS02 CS01 CS00 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero.
The Timer Counter 0 – TCNT0 Bit 7 $32 MSB 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LSB TCNT0 The Timer/Counter0 is implemented as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.
ATtiny15L The Timer/Counter1 contains two Output Compare Registers, OCR1A and OCR1B, as the data source to be compared with the Timer/Counter1 contents. In Normal mode the Output Compare function is operational with OCR1A only, and the Output Compare function includes optional clearing of the counter on compare match, and action on the Output Compare pin (PB1) (OC1A). In PWM mode OCR1A provides the data value against which the Timer/Counter value is compared. Upon compare match the PWM output is generated.
• Bits 3, 2, 1, 0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 11. Timer/Counter1 Prescale Select CS13 CS12 CS11 CS10 Description 0 0 0 0 Timer/Counter1 is stopped.
ATtiny15L Timer/Counter1 Output Compare RegisterA – OCR1A Bit 7 $2E MSB 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LSB OCR1A The Output Compare Register 1A is an 8-bit read/write register. The Timer/Counter Output Compare Register 1A contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match occurs only if Timer/Counter1 counts to the OCR1A value.
Figure 22. Effects of Unsynchronized OCR Latching Compare Value Changes Counter Value Compare Value PWM Output OC1A Synchronized OC1A Latch Compare Value Changes Counter Value Compare Value PWM Output OC1A Glitch Unsynchronized OC1A Latch During the time between the write and the latch operation, a read from OCR1A will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A.
ATtiny15L The frequency of the PWM will be Timer Clock Frequency divided by OCR1B value + 1. Table 14.
The Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. This is the typical value at VCC = 5V. See “Typical Characteristics” on page 66 for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted from 16 to 2,048 ms, as shown in Table 15. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period.
ATtiny15L 1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical “0” to WDE. This disables the Watchdog. • Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler Bits 2, 1, and 0 The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 4.6 - 8.2 ms, depending on the frequency of the calibrated RC Oscillator. See Table 16 for details. A self-timing function however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down.
ATtiny15L The EEPROM Control Register – EECR Bit 7 6 5 4 3 2 1 0 $1C – – – – EERIE EEMWE EEWE EERE Read/Write R R R R R/W R/W R/W R/W Initial value 0 0 0 0 0 0 X 0 EECR • Bit 7..4 – RES: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bits in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O Registers, the write operation will be interrupted and the result is undefined. The calibrated oscillator is used to time EEPROM. In Table 16 the typical programming time is listed for EEPROM access from the CPU. Table 16.
ATtiny15L The Analog Comparator The Analog Comparator compares the input values on the positive pin PB0 (AIN0) and negative pin PB1 (AIN1). When the voltage on the positive pin PB0 (AIN0) is higher than the voltage on the negative pin PB1 (AIN1), the Analog Comparator Output (ACO) is set (one). The comparator’s output can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select interrupt triggering on comparator output rise, fall or toggle.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and will always read as zero. • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine the comparator events that trigger the Analog Comparator Interrupt.
ATtiny15L The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages Features • • • • • • • • • • • • • • • 10-bit Resolution ±2 LSB Absolute Accuracy 0.5 LSB Integral Non-linearity Optional Offset Cancellation 65 - 260 µs Conversion Time Up to 15 kSPS 4 Multiplexed Single-ended Input Channels 1 Differential Input Channel with Optional Gain of 20x 2.56V Internal Voltage Reference 0 - 2.
Figure 25. Analog-to-Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADFR ADEN ADSC MUX1 9 ADC CTRL. & STATUS REGISTER (ADCSR) MUX0 MUX2 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS PRESCALER VCC AREF GAIN SELECTION CHANNEL SELECTION MUX DECODER INTERNAL 2.
ATtiny15L mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR bit in ADCSR selects between the two available modes. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering Power-saving sleep modes.
the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. If differential channels are selected, the conversion will only start at every other rising edge of the ADC clock cycle after ADEN was set. A normal conversion takes 13 ADC clock cycles.
ATtiny15L Figure 28. ADC Timing Diagram, Single Conversion Next Conversion Extended Conversion Cycle Number 1 2 13 12 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample & Hold MUX and REFS Update Figure 29.
ADC Noise Canceler Function The ADC features a noise canceler that enables conversion during ADC Noise Reduction mode (see “Sleep Modes” on page 23) to reduce noise induced from the CPU core and other I/O peripherals. If other I/O peripherals must be active during conversion, this mode works equivalently for Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting.
ATtiny15L • Bits 4..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bits 2..0 – MUX2..MUX0: Analog Channel and Gain Selection Bits 2..0 The value of these bits selects which analog input is connected to the ADC. In case of differential input (PB3 - PB4), gain selection is also made with these bits. Selecting PB3 as both inputs to the differential gain stage enables offset measurements. Refer to Table 20 for details.
channel must be selected before entering Free Running mode. Selecting an active channel after entering Free Running mode may result in undefined operation from the ADC. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the Ibit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector.
ATtiny15L The ADC Data Register – ADCL and ADCH ADLAR = 0 Bit 15 14 13 12 11 10 9 8 $05 – – – – – – ADC9 ADC8 ADCH $04 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 Read/Write Initial Value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLAR = 1 Bit 15 14 13 12 11 10 9 8 $05 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH $04 ADC1 ADC0 – – – – – – ADCL 7 6 5 4 3 2 1 0 Re
ADC Noise-canceling Techniques Digital circuitry inside and outside the ATtiny15L generates EMI, which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATtiny15L and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. 2.
ATtiny15L I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port B is a 6-bit bi-directional I/O port.
PORT B as General Digital I/O The lower five pins in Port B are equal when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated.
ATtiny15L • MISO/OC1A/AIN1 – PORT B, Bit 1 In Serial Programming mode, this pin serves as the serial data output, MISO. In Normal mode, this pin can serve as Timer/Counter1 output compare match output (OC1A). See the Timer/Counter1 description for further details, and how to enable the output. The OC1A pin is also the output pin for PWM mode timer function. This pin also serves as the negative input of the On-chip Analog Comparator.
Memory Programming Program and Data Memory Lock Bits The ATtiny15L MCU provides two Lock bits that can be left unprogrammed, “1”, or can be programmed, “0”, to obtain the additional features listed in Table 23. The Lock bits can only be erased with the Chip Erase command. Table 23. Lock Bit Protection Modes Memory Lock Bits Fuse Bits Mode LB1 LB2 Protection Type 1 1 1 No memory lock features enabled. 2 0 1 Further programming of the Flash and EEPROM is disabled.
ATtiny15L Calibration Byte The ATtiny15L has a one-byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address $000 in the signature address space. To make use of this byte, it should be read from this location and written into the normal Flash Program memory. At start-up, the user software must read this Flash location and write the value to the OSCCAL Register.
High-voltage Serial Programming Algorithm To program and verify the ATtiny15L in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 25): 1. Power-up sequence: Apply 4.5 - 5.5V between VCC and GND. Set PB5 and PB0 to “0” and wait at least 30 µs. Set PB3 to “0”. Wait at least 100 ns. Apply 12V to PB5 and wait at least 100 ns before changing PB0. Wait 8 µs before giving any instructions. 2.
ATtiny15L Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L(1) Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.
Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L(1) (Continued) Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.
ATtiny15L High-voltage Serial Programming Characteristics Figure 32. High-voltage Serial Programming Timing VALID SDI (PB0), SII (PB1) tSHIX t SHSL tIVSH tSLSH SCI (PB3) 1 2 7 8 9 10 15 16 SDO (PB2) tSHOV Internal CK Table 26. High-voltage Serial Programming Characteristics, TA = 25°C ± 10%, VCC = 5.0V ± 10% (unless otherwise noted) Symbol Low-voltage Serial Downloading Parameter Min Typ tSHSL SCI (PB3) Pulse Width High 25.0 ns tSLSH SCI (PB3) Pulse Width Low 25.
The device is clocked from the internal clock at the uncalibrated minimum frequency (0.8 - 1.6 MHz). The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 MCU clock cycles High: > 2 MCU clock cycles Low-voltage Serial Programming Algorithm When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK. When reading data from the ATtiny15L, data is clocked on the falling edge of SCK. See Figure 34, Figure 35, and Table 28 for timing details.
ATtiny15L Data Polling When a byte is being programmed into the Flash or EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF so when programming this value, the user will have to wait for at least tWD_PROG_FL before programming the next Flash byte, or tWD_PROG_EE before the next EEPROM byte.
Table 27. Low-voltage Serial Programming Instruction Set(1) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming while RESET is low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase Flash and EEPROM memory arrays. Read Program Memory 0010 H000 xxxx xxxa bbbb bbbb oooo oooo Read H (high or low) data o from program memory at word address a:b.
ATtiny15L Low-voltage Serial Programming Characteristics Figure 35. Low-voltage Serial Programming Timing MOSI tOVSH SCK tSHOX tSLSH tSHSL MISO tSLIV Table 28. Low-voltage Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7 - 5.5V (Unless Otherwise Noted) Symbol Parameter Min Typ 1/tCLCL RC Oscillator Frequency (VCC = 2.7 - 5.5V) 0.8 1.6 tCLCL RC Oscillator Period (VCC = 2.7 - 5.5V) tSHSL SCK Pulse Width High 2.0 tCLCL ns tSLSH SCK Pulse Width Low 2.
Electrical Characteristics Absolute Maximum Ratings Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin Except RESET with Respect to Ground ............................. -1.0V to VCC + 0.5V Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATtiny15L DC Characteristics (Continued) TA = -40°C to 85°C, VCC = 2.7V to 5.5V Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V VIN = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V VIN = VCC/2 TACID Analog Comparator Initialization Delay VCC = 2.7V VCC = 4.0V Note: Min Typ -50.0 750.0 500.0 Max Units 40.0 mV 50.0 nA ns 1. “Max” means the highest value where the pin is guaranteed to be read as low. 2.
Typical Characteristics The following charts show typical behavior. These data are characterized but not tested. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. The current consumption is a function of several factors such as: Operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.
ATtiny15L Figure 37. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 1.6MHz INTERNAL RC OSCILLATOR 3 TA = 85˚C 2.5 TA = 25˚C I cc(mA) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Frequency Relative to Nominal Frequency at 25˚C and VCC = 5.0V Figure 38. Calibrated Internal RC Oscillator Frequency vs. VCC Relative Calibrated RC Oscillator Frequency vs. Operating Voltage 1.02 TA = 25 ˚C 25˚C TA = 45˚C TA = 70˚C 1.00 TA = 85˚C 0.98 0.96 0.94 0.92 0.90 0.88 2 2.
Figure 39. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. Vcc MEASURED WITH ANALOG COMPARATOR 1.301 TA = 25˚C 1.3 TA = 45˚C 1.299 TA = 70˚C 1.298 TA = 85˚C VBG (V) 1.297 1.296 1.295 1.294 1.293 1.292 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 40. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 18 16 TA = 25˚C Offset Voltage (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATtiny15L Figure 41. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. Vcc = 2.7V COMMON MODE VOLTAGE 10 TA = 25˚C Offset Voltage (mV) 8 6 TA = 85˚C 4 2 0 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Figure 42. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 30 I ACLK (nA) 40 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.
Figure 43. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. Vcc 1600 1400 TA = 25˚C 1200 TA = 85˚C F RC (KHz) 1000 800 600 400 200 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 6 Vcc (V) Note: 1. Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 44. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 120 TA = 25˚C 100 TA = 85˚C I OP (µA) 80 60 40 20 0 0 70 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.
ATtiny15L Figure 45. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 30 TA = 25˚C 25 TA = 85˚C 15 I OP (µA) 20 10 5 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 46. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 70 TA = 25˚C 60 TA = 85˚C 50 30 I OL (mA) 40 20 10 0 0 0.5 1 1.5 2 2.
Figure 47. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 20 TA = 25˚C 18 16 TA = 85˚C 14 I OH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOH (V) Figure 48. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 25 TA = 25˚C 20 TA = 85˚C 10 I OL (mA) 15 5 0 0 0.5 1 1.
ATtiny15L Figure 49. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25˚C 5 TA = 85˚C 3 I OH (mA) 4 2 1 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 50. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25˚C 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.
Figure 51. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25˚C 0.18 0.16 Input hysteresis (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.
ATtiny15L ATtiny15L Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F SREG I T H S V N Z C page 11 $3E Reserved $3C Reserved $3B GIMSK - INT0 PCIE - - - - - page 19 $3A GIFR - INTF0 PCIF - - - - - page 20 $39 TIMSK - OCIE1A - - - TOIE1 TOIE0 - page 20 $38 TIFR - OCF1A - - - TOV1 TOV0 - page 21 $37 Reserved $36 Reserved $35 MCUCR - PUD SE SM1 SM0 - ISC01 ISC00 page 22 $34 MCUSR - - -
ATtiny15L Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry Two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Car
ATtiny15L ATtiny15L Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0 None # Clocks 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left through Carry Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7) Z,C,N,V 1 ROR Rd Rotate Right through Carry Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0) Z,C,N,V 1 ASR Rd Arithmetic S
Ordering Information Power Supply Speed (MHz) Ordering Code Package Operation Range 2.7 - 5.5V 1.6 ATtiny15L-1PC ATtiny15L-1SC 8P3 8S2 Commercial (0°C to 70°C) ATtiny15L-1PI ATtiny15L-1SI 8P3 8S2 Industrial (-40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.
ATtiny15L Packaging Information 8P3 8P3, 8-lead, Plastic Dual Inline Package (PDIP), 0.300" Wide. Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-001 BA 10.16(0.400) 9.017(0.355) PIN 1 7.11(0.280) 6.10(0.240) .300 (7.62) REF 254(0.100) BSC 5.33(0.210) MAX Seating Plane 3.81(0.150) 2.92(0.115) 1.78(0.070) 1.14(0.045) 0.381(0.015)MIN 0.559(0.022) 0.356(0.014) 4.95(0.195) 2.92(0.115) 8.26(0.325) 7.62(0.300) 0.356(0.014) 0.203(0.008) 1.524(0.060) 0.000(0.000) 10.90(0.
8S2 1 H N Top View e b A D COMMON DIMENSIONS (Unit of Measure = mm) Side View SYMBOL MIN NOM MAX NOTE C A1 L E End View A 1.78 2.03 A1 0.05 0.33 b 0.35 0.51 5 C 0.18 0.25 5 D 5.13 5.38 E 5.13 5.41 2, 3 H 7.62 8.38 L 0.51 e 0.89 1.27 BSC 4 Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3.
ATtiny15L Table of Contents Features................................................................................................. 1 Pin Configuration.................................................................................. 1 Description ............................................................................................ 2 Block Diagram ...................................................................................................... 3 Pin Descriptions...............................
I/O Port B ............................................................................................. 51 Memory Programming........................................................................ 54 Program and Data Memory Lock Bits................................................................. Fuse Bits............................................................................................................. Signature Bytes ............................................................................
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