Owner's manual

ATtiny15L

1187E–AVR–06/02

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana-

log Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny15L and will always read as zero.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine the comparator events that trigger the Analog Comparator Inter-

rupt. The different settings are shown in Table 17.

Note: 1. When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt

can occur when the bits are changed.

Table 17. ACIS1/ACIS0 Settings

(1)

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

01Reserved

1 0 Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge