Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-Volatile Program and Data Memories – 4K Bytes of In-System Programmable Program Memory Flash – 64 Bytes of In-System Programmable EEPROM – 256 Bytes of Internal SRAM – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/ 100 ye
1. Pin Configurations Figure 1-1.
capability except PA7 which has the RESET capability. To use pin PA7 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.
2. Overview The ATtiny43U is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny43U achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1.
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
3. About 3.1 Resources A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.2 Architectural Overview Figure 4-1.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
4.4.1 SREG - AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
Figure 4-3. The X-, Y-, and Z-registers 15 X-register XH 7 XL 0 R27 (0x1B) 15 Y-register 0 R26 (0x1A) YH 7 YL 0 R29 (0x1D) Z-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.
4.6.1 SPH and SPL — Stack Pointer Register Bit 4.
4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors.
Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<
5. Memories 5.1 Overview This section describes the different memories in ATtiny43U. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny43U features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.2 In-System Re-programmable Flash Program Memory The ATtiny43U contains 4K byte On-chip In-System Reprogrammable Flash memory for program storage.
The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 256 bytes of internal data SRAM in ATtiny43U are all accessible through all these addressing modes.
the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see “Serial Programming” on page 151. 5.4.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken.
data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations. The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on page 28. The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
5.5 I/O Memory The I/O space definition of the ATtiny43U is shown in “Register Summary” on page 167. All I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
5.6.2 EEDR – EEPROM Data Register Bit 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x1D (0x3D) EEDR • Bits 7:0 – EEDR[7:0]: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. • Bit 1 – EEPE: EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.
6. System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 31. The clock systems are detailed below. Figure 6-1.
6.1.4 6.2 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1.
When this clock source is selected, start-up times are determined by SUT Fuses as shown in Table 6-3. Table 6-3. Start-up Times for the External Clock Selection SUT1..
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-5 below. Table 6-5. SUT1..0 Start-up times for Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power-down Additional Delay from Reset (VCC = 5.0V) (1) 00 6 CK 01 6 CK 14CK + 4 ms Fast rising power 10(2) 6 CK 14CK + 64 ms Slowly rising power 11 Note: 14CK Recommended Usage BOD enabled Reserved 1.
6.2.5 Clock Startup Sequence Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be considered stable. To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by all other reset sources. The section “System Control and Reset” on page 48 describes the start conditions for the internal reset.
it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. 6.4 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system.
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
7. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See “Software BOD Disable” on page 32 for more details. 7.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the “ACSR – Analog Comparator Control and Status Register” on page 113. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When the SM1..
peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped 7.4 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system.
7.4.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
Table 7-2. Sleep Mode Select SM1 SM0 Sleep Mode 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Reserved • Bit 2 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 7.5.
8. Power Supply and On-Chip Boost Converter In order to work properly microcontrollers typically require a supply voltage level that can not be provided by battery packs of less than two or three battery cells. This constraint adds to size, cost and complexity of the design. The integrated boost converter of ATtiny43U bridges the gap between minimum supply voltage of the device and typical output voltages of single-cell standard, alkaline, Lithium, NiCd or NiMH batteries.
Figure 8-2. C4 Typical Connection of Boost Converter. C3 PB0 PB1 PA7 PA6 PB2 PB3 PB4 PB5 PA5 PA4 PA3 PA2 PB6 PB7 VCC PA1 PA0 VBAT GND LSW R1 VIN C2 C1 D1 L1 When the boost converter is not connected the microcontroller can be powered directly from an external source and is then subject to the standard supply voltage limits defined in “Electrical Characteristics” on page 155. It is recommended to disable the Brown-Out Detection (BOD) circuit when using the integrated boost converter.
8.2.1 Stop Mode The boost converter enters Stop Mode (see Figure 8-3 on page 37 for modes of operation) when input voltage ,VBAT, is below the shutdown voltage, VSTOP (see Table 20-7 on page 159). Alternatively, the boost converter enters Stop Mode when instructed by firmware to do so. In this mode of operation the boost converter is not active and current consumption is decreased to a minimum. This is in order to prevent battery discharge and to avoid battery damage.
Figure 8-4. Input and Output Voltages of Boost Converter. VCC VBAT VPOT VSTART VBOOST VSTOP t CONVERTER: MCU CORE: STOP RESET ACTIVE ACTIVE STOP RESET When input voltage VBAT falls below VSTOP the converter enters Stop Mode and output voltage VCC begins to fall. When converter output voltage, i.e. the supply voltage of the microcontroller, falls below VPOT the MCU will go into reset. Figure 8-5 illustrates how the boost converter output changes with load current.
As current consumption goes below IMS (see Figure 8-5) the converter goes from Active Regulated Mode to Active Low Current Mode. After this, the more the load current is decreased the longer the discharge time of the output capacitor, i.e. the time when the converter is not switching, will be. Similarly, the charge time, i.e. the time when the converter is switching, will be shorter. Note that in Active Low Current Mode only the last part of the rising/switching slope is changed.
Figure 8-6. Typical Output Voltage of Boost Converter in Active Regulated Mode. VCC OD E ACTIVE REGULATED MODE STA RT M VRPP fSW t 8.3.2 Active Low Current Mode The boost converter enters Active Low Current Mode from Active Regulated Mode when output voltage reaches its maximum and duty cycle is at its minimum. In practice, this means that the load current drops below a threshold.
Figure 8-7. Typical Output Voltage of Boost Converter at Constant Full Duty Cycle. VCC FDC = ON BL E VA RI A FULL FDC = OFF DUTY CYCLE See section “Software Control of Boost Converter” on page 42 for instructions on how to turn on and off duty cycle control. The use of Full Duty Cycle mode is recommended only at low load currents. 8.4 Overload Behaviour The output is considered overloaded when the load current, ILOAD, exceeds the maximum given in Table 20-7 on page 159.
To stop the boost converter, follow the below procedure: 1. Write 110x xxxx to the Power Reduction Register, PRR 2. Within 3 clock cycles of the above, write 10xx xxxx to PRR 3. Within 4 clock cycles of the first step, write 01xx xxxx to PRR 8.5.2 Switching to Full Duty Cycle Mode of Operation When duty cycle control is disabled the output voltage of the boost converter will rise as fast as possible, resulting in a minimum switching time and a maximum idle time for the converter.
... where D is the duty cycle and TS the switching period of the boost converter. See “Boost Converter Characteristics” on page 159 for limits. The steady-state duty cycle is calculated as follows: V CC 1⎞ D = ⎛ ------------ – --- × I LOAD ⎝V 2⎠ BAT Overall efficiency of the boost converter is also affected by the resistance of the inductor. 8.6.2 Diode It is recommended to use a Schottky diode with forward voltage, VF, and reverse leakage current, IR, values as low as possible.
Too high resistor values may lead to Start Mode failures. See “Boost Converter Component Values” on page 45 for component recommendations and limits. Capacitor C2 should be located close to the device. 8.6.5 Output Capacitors An output capacitor, C3, is required to keep the output voltage stable at times when energy is transferred to the inductor. It is recommended to use a capacitor with high capacitance and low Equivalent Series Resistance, ESR.
8.7 Typical Applications A typical use of the boost converter is illustrated in Figure 8-2 on page 37. Components can be optimized depending on the type of application. Table 8-2, below, presents recommendations for three different types of applications (cost effective, high output current and long battery life). All values are guidelines, only. Table 8-2.
boost converter, connect pins V BAT and LSW to ground and provide the device with supply directly to the VCC pin. 8.11 8.11.1 Register Description ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 0x03 (0x23) BS ACME – ADLAR – ADTS2 ADTS1 ADTS0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7 – BS: Boost Status The BS bit can be used to identify silent periods of the boost converter.
9. System Control and Reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 9-1 shows the reset logic.
9.2 Reset Sources The ATtiny43U has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled. • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. • Brown-out Reset.
9.4 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see Table 20-4 on page 158) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 9-4. External Reset During Operation CC 9.
It is recommended to disable the BOD when using the integrated boost converter. See “Power Supply and On-Chip Boost Converter” on page 36 9.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See “Watchdog Timer” on page 51 for details on operation of the Watchdog Timer. Figure 9-6. Watchdog Reset During Operation CC CK 9.
clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny43U resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 9-3 on page 56. The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down.
9.8.1.2 Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2.
9.9 9.9.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs.
the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 9-2. Watchdog Timer Configuration WDE WDIE Watchdog Timer State Action on Time-out 0 0 Stopped None 0 1 Running Interrupt 1 0 Running Reset 1 1 Running Interrupt • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
• Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1, and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 9-3 on page 56. Table 9-3. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
10. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny43U. For a general explanation of the AVR interrupt handling, see “Reset and Interrupt Handling” on page 13. 10.1 Interrupt Vectors Table 10-1. Reset and Interrupt Vectors Vector No.
0x0008 rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x0009 rjmp TIM0_COMPB ; Timer0 Compare B Handler 0x000A rjmp TIM0_OVF ; Timer0 Overflow Handler 0x000B rjmp ANA_COMP ; Analog Comparator Handler 0x000C rjmp ADC ; ADC Conversion Handler 0x000D rjmp EE_RDY ; EEPROM Ready Handler 0x000E rjmp USI_STR ; USI Start Handler 0x000F rjmp USI_OVF ; USI Overflow Handler ; 0x0010 RESET: ldi 0x0011 out 0x0012 0x0013 ... 10.
Figure 10-1. Timing of pin change interrupts pin_lat PCINT(0) D pcint_in_(0) Q clk 0 pcint_syn pcint_setflag PCIF pin_sync LE x PCINT(0) in PCMSK(x) clk clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 10.3 10.3.1 Register Description MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 10-2. 10.3.
• Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.
11. I/O Ports 11.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
11.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 11-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 11-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx SLEEP WPx RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 11.2.
be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 11.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Figure 11-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 11.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level.
Figure 11-5.
Table 11-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 11-5 on page 68 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 11-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
11.3.1 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 11-3 on page 70. Table 11-3. Port A Pins Alternate Functions Port Pin Alternate Function PA0 ADC0: ADC input channel 0. PCINT0:Pin change interrupt 0 source 0. PA1 ADC1: ADC input channel 1. PCINT1:Pin change interrupt 0 source 1. PA2 ADC2: ADC input channel 2. PCINT2: Pin change interrupt 0 source 2. PA3 ADC3: ADC input channel 3. PCINT3: Pin change interrupt 0 source 3.
• Port A, Bit 4 – AIN0/PCINT4 AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT4: Pin Change Interrupt source 4. The PA4 pin can serve as an external interrupt source for pin change interrupt 0. • Port A, Bit 5 – AIN1/PCINT5 AIN1: Analog Comparator Negative Input.
Table 11-4 on page 72 to Table 11-6 on page 73 relate the alternate functions of Port A to the overriding signals shown in Figure 11-5 on page 68. Table 11-4. Signal Name Overriding Signals for Alternate Functions in PA7..
Table 11-6. Overriding Signals for Alternate Functions in PA3..PA2 Signal Name PA3/ADC3/PCINT3 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 0 PTOE 0 0 DIEOE (PCINT3 • PCIE0) + ADC3D (PCINT2 • PCIE) + ADC2D DIEOV PCINT3 • PCIE0 PCINT2 • PCIE0 DI PCINT3 Input PCINT2 Input AIO ADC3 Input ADC2 Table 11-7. PA2/ADC2/PCINT2 0 0 Overriding Signals for Alternate Functions in PA1..
11.3.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 11-8 on page 74. Table 11-8. Port B Pins Alternate Functions Port Pin Alternate Function PB0 T0: Timer/Counter0 Counter Source. PCINT8: Pin change interrupt 1 source 8. PB1 OC0A: Timer/Counter0 Compare Match A output. PCINT9: Pin change interrupt 1 source 9. PB2 OC0B: Timer/Counter0 Compare Match B output. PCINT10:Pin change interrupt 1 source 10. PB3 T1: Timer/Counter1 Counter Source.
PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt source for pin change interrupt 1. • Port B, Bit 3 – T1/CLKO/PCINT11 T1: Timer/Counter1 Counter source. CLKO: System Clock Output. The system clock can be output on the PB3 pin. The system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB3 and DDB3 settings. It will also be output during reset. PCINT11: Pin Change Interrupt source 11.
Table 11-9 on page 76 to Table 11-12 on page 77 relate the alternate functions of Port B to the overriding signals shown in Figure 11-5 on page 68. Table 11-9. Overriding Signals for Alternate Functions in PB7..
Table 11-11. Overriding Signals for Alternate Functions in PB3..PB2 Signal Name PB3/T1/CLKO/PCINT9 PB2/OC0B/PCINT8 PUOE CKOUT 0 PUOV 0 0 DDOE CKOUT 0 DDOV 1’b1 0 PVOE CKOUT OC0B Enable PVOV CKOUT • System Clock OC0B PTOE 0 0 DIEOE PCINT9 • PCIE1 PCINT8 • PCIE1 DIEOV PCINT9 • PCIE1 PCINT8 • PCIE1 DI T1/PCINT9 Input PCINT8 Input AIO Table 11-12. Overriding Signals for Alternate Functions in PB1..
11.4 11.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
12. 8-bit Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1) 12.1 Features • • • • • • • 12.
12.2.1 Registers The Timer/Counter (TCNTn) and Output Compare Registers (OCRnA and OCRnB) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin.
Figure 12-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count Increment or decrement TCNTn by 1. direction Select between increment and decrement. clear Clear TCNTn (set all bits to zero). clkTn Timer/Counter clock, referred to as clkTn in the following. top Signalize that TCNTn has reached maximum value.
Figure 12-3. Output Compare Unit, Block Diagram DATA BUS TCNTn OCRnx = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCRnx Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Registers to either top or bottom of the counting sequence.
generation. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is down-counting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCnx value is to use the Force Output Compare (nx) strobe bits in Normal mode. The OCnx Registers keep their values even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
The design of the Output Compare pin logic allows initialization of the OCnx state before the output is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation, see “Register Description” on page 90 12.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in Normal, CTC, and PWM modes.
The timing diagram for the CTC mode is shown in Figure 12-5 on page 85. The counter value (TCNTn) increases until a Compare Match occurs between TCNTn and OCRnA, and then counter (TCNTn) is cleared. Figure 12-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCFnA Flag.
for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-6 on page 86.
in a constantly high or low output (depending on the polarity of the output set by the COMnA1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnx to toggle its logical level on each Compare Match (COMnx1:0 = 1). The waveform generated will have a maximum frequency of fOCnx = fclk_I/O/2 when OCRnA is set to zero.
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM.
Figure 12-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 12-9 on page 89 shows the same timing data, but with the prescaler enabled. Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 12-10 on page 89 shows the setting of OCFnB in all modes and OCFnA in all modes except CTC mode and PWM mode, where OCRnA is TOP. Figure 12-10.
Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 12.9 12.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 12.9.
Table 12-3 on page 91 shows the COMnA[1:0] bit functionality when the WGMn[1:0] bits are set to fast PWM mode. Table 12-3. Compare Output Mode, Fast PWM Mode(1) COMnA1 COMnA0 0 0 Normal port operation, OCnA disconnected. 0 1 WGMn2 = 0: Normal Port Operation, OCnA Disconnected. WGMn2 = 1: Toggle OCnA on Compare Match. 1 0 Clear OCnA on Compare Match, set OCnA at TOP 1 1 Set OCnA on Compare Match, clear OCnA at TOP Note: Description 1.
Table 12-6 on page 92 shows the COMnB[1:0] bit functionality when the WGMn[2:0] bits are set to fast PWM mode. Table 12-6. Compare Output Mode, Fast PWM Mode(1) COMnB1 COMnB0 0 0 Normal port operation, OCnB disconnected. 0 1 Reserved 1 0 Clear OCnB on Compare Match, set OC0B at TOP 1 1 Set OCnB on Compare Match, clear OC0B at TOP Note: Description 1. A special case occurs when OCRnB equals TOP and COMnB1 is set.
Table 12-8. TOP Update of OCRx at TOV Flag Set on(1) WGMn2 WGMn1 WGMn0 0 0 0 0 Normal 0xFF Immediate MAX 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRnA Immediate MAX 3 0 1 1 Fast PWM 0xFF TOP MAX 4 1 0 0 Reserved – – – 5 1 0 1 PWM, Phase Correct OCRnA TOP BOTTOM 6 1 1 0 Reserved – – – 7 1 1 1 Fast PWM OCRnA TOP TOP 1. MAX = 0xFF, BOTTOM = 0x00 TCCR0B – Timer/Counter Control Register B Bit 12.9.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOCnB bit, an immediate Compare Match is forced on the Waveform Generation unit. The OCnB output is changed according to its COMnB1:0 bits setting. Note that the FOCnB bit is implemented as a strobe. Therefore it is the value present in the COMnB1:0 bits that determines the effect of the forced compare.
12.9.6 TCNT1 – Timer/Counter Register Bit 7 6 5 4 0x2D (0x4D) 3 2 1 0 TCNT1[7:0] TCNT1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNTn Register blocks (removes) the Compare Match on the following timer clock.
12.9.12 TIMSK1 – Timer/Counter 1 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x0C (0x2C) – – – – – OCIE1B OCIE1A TOIE1 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK1 • Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read zero.
• Bit 1 – OCFnA: Output Compare Flag n A The OCFnA bit is set when a Compare Match occurs between the Timer/Countern and the data in OCRnA – Output Compare Registern A. OCFnA is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCFnA is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIEnA (Timer/Countern Compare Match Interrupt Enable), and OCFnA are set, the Timer/Countern Compare Match Interrupt is executed.
13. Timer/Counter Prescaler Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counters. Tn is used as a general name, n = 0, 1. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
14. USI – Universal Serial Interface 14.1 Features • • • • • • 14.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication.
output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete.
Figure 14-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The three-wire mode timing is shown in Figure 14-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
SPITransfer_loop: out USICR,r17 in r16, USISR sbrs r16, USIOIF rjmp SPITransfer_loop in r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16.
14.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
Figure 14-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER The data direction is not given by the physical layer. A protocol, like the one used by the TWIbus, must be implemented to control the data flow. Figure 14-5.
detects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary. 2. In addition, the start detector will hold the SCL line low after the master has forced a negative edge on this line (B). This allows the slave to wake up from sleep or complete other tasks before setting up the USI Data Register to receive the address. This is done by clearing the start condition flag and resetting the counter. 3.
14.4 Alternative USI Usage The flexible design of the USI allows it to be used for other tasks when serial communication is not needed. Below are some examples. 14.4.1 Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher performance UART than by software, only. 14.4.2 4-Bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
nally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in Table 14-1. Table 14-1. Relationship between USIWM[1:0] and USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operate as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORTA register. However, the corresponding DDRA bit still controls the data direction.
Table 14-2 shows the relationship between the USICS[1:0] and USICLK setting and clock source used for the USI Data Register and the 4-bit counter. Table 14-2.
If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be generated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in two-wire mode. A start condition interrupt will wakeup the processor from all sleep modes. • Bit 6 – USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0).
Note that even when no wire mode is selected (USIWM[1:0] = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register. The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input is sampled and data output is changed on opposite clock edges.
15. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
Table 15-1. 15.2 15.2.1 Analog Comparator Multiplexed Input ACME ADEN MUX2..
• Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
16. Analog to Digital Converter 16.1 Features • • • • • • • • • • • • • • 16.2 10-bit Resolution 1 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13µs Conversion Time 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Temperature Sensor Input Channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 1.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. The analog multiplexer allows eight single-ended channels to be connected to the ADC, including the low four bits of port A, the internal temperature sensor, the internal voltage reference, supply voltage (VBAT) and ground (GND). Internal reference voltage of nominally 1.1V is provided on-chip. Alternatively, VCC can be used as reference voltage. 16.
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored.
Figure 16-3. ADC Prescaler ADEN START Reset 7-BIT ADC PRESCALER CK/64 CK/128 CK/32 CK/8 CK/16 CK/4 CK/2 CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles, as summarised in Table 16-1 on page 120.
Figure 16-5. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 16-6 below. This assures a fixed delay from the trigger event to the start of conversion.
Figure 16-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update For a summary of conversion times, see Table 16-1. Table 16-1. ADC Conversion Time Condition Sample & Hold (Cycles from Start of Conversion) First conversion 13.5 25 Normal conversions 1.5 13 2 13.5 2.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: • When ADATE or ADEN is cleared. • During conversion, minimum one ADC clock cycle after the trigger event. • After a conversion, before the Interrupt Flag used as trigger source is cleared.
conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not automatically be turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 16.8 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 16-8.
• Keep analog tracks well away from high-speed switching digital tracks. • Use the ADC noise canceler function to reduce induced noise from the CPU. • If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress. • Place bypass capacitors as close to VCC and GND pins as possible. Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as described in Section 16.7 on page 121.
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 16-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 16-11.
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 16-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
perature sensor is enabled, the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor. The measured voltage has a linear relationship to the temperature as described in Table 16-2 The sensitivity is approximately 1 LSB / °C and the accuracy depends on the method of user calibration. Typically, the measurement accuracy after a single temperature calibration is ±10°C, assuming calibration at room temperature.
• Bits 2:0 – MUX[2:0]: Analog Channel Selection Bits The value of these bits selects which analog input is connected to the ADC, as shown in Table 16-4. Selecting channel ADC4 enables temperature measurement. Table 16-4. ADC Multiplexer Channel Selections. Single Ended Input MUX[2:0] ADC0 (PA0) 000 ADC1 (PA1) 001 ADC2 (PA2) 010 ADC3 (PA3) 011 0V (GND) 100 1.1V (I Ref) 101 VBAT (1) 110 (2) 111 ADC4 Notes: 1.
• Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI instruction is used.
When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted.
Table 16-6. 16.13.
17. debugWIRE On-chip Debug System 17.1 Features • • • • • • • • • • 17.
When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 17.
18. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”). The Program memory is updated in a page by page fashion.
18.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. 18.4 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
18.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 18.6 Reading the Fuse and Lock Bits from Software It is possible for firmware to read device fuse and lock bits.
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 Refer to Table 19-4 on page 140 for detailed description and mapping of the Fuse High Byte. To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure.
18.7 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
• Bit 3 – RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “EEPROM Write Prevents Writing to SPMCSR” on page 135 for details.
19. Memory Programming This section describes the different methods for Programming the ATtiny43U memories. 19.1 Program And Data Memory Lock Bits The ATtiny43U provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 19-2 on page 139. The Lock bits can only be erased to “1” with the Chip Erase command. The device has no separate boot loader section.
19.2 Fuse Bytes The ATtiny43U has three Fuse bytes. Table 19-3, Table 19-4 and Table 19-5 briefly describe the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.. Table 19-3.
Table 19-5. Fuse Low Byte Fuse Low Byte Bit No (1) Description Default Value CKDIV8 7 Divide clock by 8 0 (programmed) CKOUT 6 Clock Output Enable 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(2) SUT0 4 Select start-up time 0 (programmed)(2) CKSEL3 3 Select Clock source 0 (programmed)(3) CKSEL2 2 Select Clock source 0 (programmed)(3) CKSEL1 1 Select Clock source 1 (unprogrammed)(3) CKSEL0 0 Select Clock source 0 (programmed)(3) Notes: 1.
19.3.1 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. Signature bytes can also be read by the device firmware. See section “Reading the Fuse and Lock Bits from Software” on page 135. The three signature bytes reside in a separate address space called the device signature imprint table. The signature data for ATtiny43U is given in Table 19-7.
Figure 19-1. Parallel Programming +5V WR PA0 XA0 PA1 XA1/BS2 PA2 PAGEL/BS1 PA3 OE PA4 RDY/BSY PA5 VCC PB7 - PB0 DATA CLKI/PA6 +12 V RESET/PA7 GND Table 19-10. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O WR PA0 I Write Pulse (Active low). XA0 PA1 I CLKI Action Bit 0 XA1/BS2 PA2 I CLKI Action Bit 1. Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte). PAGEL/BS1 PA3 I Byte Select 1 (“0” selects low byte, “1” selects high byte).
The XA1/XA0 pins determine the action executed when the CLKI pin is given a positive pulse. The bit coding is shown in Table 19-12. Table 19-12. XA1 and XA0 Coding XA1 XA0 Action when CLKI is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle When pulsing WR or OE, the command loaded determines the action executed.
• The command needs only be loaded once when writing or reading multiple memory locations. • Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. • Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 19.6.
1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give CLKI a positive pulse. This loads the data byte. E. No action F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 19-2 on page 147.
Figure 19-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 19-8 on page 142. Figure 19-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR.
5. E: No action. K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 19-4 for signal waveforms). Figure 19-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR.
19.6.8 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 145 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. 19.6.
1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. 19.6.
1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. 19.7 Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 19-7 below. Figure 19-7. Serial Programming and Verify +1.8 - 5.
19.7.1 Serial Programming Algorithm When writing serial data to the ATtiny43U, data is clocked on the rising edge of SCK. When reading data from the ATtiny43U, data is clocked on the falling edge of SCK. See Figure 20-6 and Figure 20-7 for timing details. To program and verify the ATtiny43U in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 19-16): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 19-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location 19.7.2 Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 4.0 ms tWD_FUSE 4.5 ms Serial Programming Instruction set Table 19-16 on page 153 and Figure 19-8 on page 154 describes the Instruction set. Table 19-16.
Table 19-16. Serial Programming Instruction Set (Continued) Instruction Format (1) Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4 Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Notes: 1. 2. 3. 4. 5. Not all instructions are applicable for all parts. a = address Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
20. Electrical Characteristics 20.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Table 20-1. Symbol RPU DC Characteristics. TA = -40°C to 85°C (Continued) Parameter Condition Pull-up Resistor, I/O Pin VCC = 5.5V, input low Pull-up Resistor, RESET Pin VCC = 5.5V, input low Supply Current, Active Mode, Without Boost Converter (7) ICC Supply Current, Idle Mode, Without Boost Converter (7) Supply Current, Power-Down Mode, Without Boost Converter (7) Notes: Min. Typ. Max. Units 20 50 kΩ 30 80 kΩ f = 1MHz, VCC = 2V 0.2 0.55 mA f = 4MHz, VCC = 3V 1.3 2.
20.4 Clock Characteristics 20.4.1 Calibrated Internal Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Please note that the oscillator frequency depends on temperature and voltage. Table 20-2. Calibration Method Calibration Accuracy of Internal Oscillator Target Frequency VCC Temperature Accuracy at given Voltage & Temperature (1) Factory Calibration 8.
20.5 System and Reset Characteristics Table 20-4. Symbol Reset, Brown-Out and Internal Voltage Characteristics Parameter Condition Min Typ Max Units TA = -40 - 85°C 1.1 1.4 1.6 V Power-on Reset Threshold Voltage (falling) TA = -40 - 85°C 0.6 1.3 1.6 V VPSR Power-On Slope Rate TA = -40 - 85°C 0.01 VRST RESET Pin Threshold tRST Minimum pulse width on RESET Pin Power-on Reset Threshold Voltage (rising) VPOT (1) V/ms 0.
20.7 Boost Converter Characteristics Table 20-7. Characteristics of Boost Converter. T = -20°C ... +85°C, unless otherwise noted Symbol Parameter VSTART Condition Min Typ Max Unit Start Voltage 1.05 1.2 1.35 V VBAT Input Voltage 0.7 1.8 V VSTOP Shutdown Voltage 0.45 0.7 V 1.0 VBOOST Active Mode, ILOAD > 1mA 2.7 Low Current Mode 3.3 V 1.8 3.6 V VBAT = 0.7V 0 10 mA VBAT = 1.0V 0 30 mA VCC Output Voltage ILOAD Load Current VRPP Output Voltage Ripple VBAT = 1.
20.8 ADC Characteristics – Preliminary Data Table 20-8. Symbol ADC Characteristics, Single_Ended Conversion, TA = -40°C - 85°C, Boost Converter Disabled. Parameter Condition Min Typ Resolution 10 Bits 4.0 TBD LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz 5.0 TBD LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 3.0 TBD LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 4.
Table 20-9. Symbol ADC Characteristics, Single_Ended Conversion, TA = -40°C - 85°C, Boost Converter Enabled.
20.9 Parallel Programming Characteristics Figure 20-3. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL CLKI tDVXH tXLDX tBVPH tPLBX t BVWL Data & Contol (DATA, XA0, XA1/BS2, PAGEL/BS1) tWLBX tWLWH WR tPLWL WLRL RDY/BSY tWLRH Note: The timing requirements in Figure 20-3 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Figure 20-4.
Figure 20-5. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) LOAD DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t XLXH CLKI PAGEL/BS1 DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Table 20-10. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
20.10 Serial Programming Characteristics Figure 20-6. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Figure 20-7. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 20-11. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Oscillator Period 1/tCLCL 164 Oscillator Frequency (VCC = 4.
21. Typical Characteristics – TBD The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
Figure 21-2. Boost Converter Efficiency vs. Load Current and VBAT Voltage BOOST CONVERTER EFFICIENCY vs. LOAD CURRENT 90 VBAT = 1.8 V 80 Efficiency (%) VBAT = 1.5 V VBAT = 1.2 V 70 VBAT = 1.0 V VBAT = 0.7 V 60 0 10 20 30 Load Current (mA) Figure 21-3. Input Voltage Required to Maintain Regulation vs. Load Current TYPICAL VBAT VOLTAGES REQUIRED TO MAINTAIN OUTPUT REGULATION 1.2 1.1 VBAT (V) 1.0 0.9 0.8 0.7 0.
22.
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
23.
Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
24. Ordering Information 24.1 ATtiny43U Speed (MHz) Power Supply 8 1.8 - 5.5V (3) Notes: Ordering Code (1) Package (2) ATtiny43U-MU ATtiny43U-SU 20M1 20S2 Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).
25. Packaging Information 25.1 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b D D2 E2 L MAX NOTE 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOM 0.20 REF 0.18 E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
25.
26. Errata The revision letter in this section refers to the revision of the ATtiny43U device. 26.1 26.1.1 ATtiny43U Rev. C • Increased Probability of Boost Converter Entering Active Low Current Mode 1. Increased Probability of Boost Converter Entering Active Low Current Mode The boost converter may enter and stay in Active Low Current Mode at supply voltages and load currents higher than those specified. This is due to high switching currents in bonding wires of the SOIC package.
27. Datasheet Revision History 27.1 Rev. 8048B-03/09 1. 27.2 Updated Data retention bullet in “Features” on page 1. Rev. 8048A-02/09 1. Initial revision.
ATtiny43U 8048B–AVR–03/09
Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 Pin Descriptions .................................................................................................2 2 Overview ................................................................................................... 4 3 About ...........................
8 9 7.1 Sleep Modes ....................................................................................................31 7.2 Software BOD Disable .....................................................................................32 7.3 Power Reduction Register ...............................................................................32 7.4 Minimizing Power Consumption ......................................................................33 7.5 Register Description .......................
11.4 Register Description ........................................................................................78 12 8-bit Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1) . 79 12.1 Features ..........................................................................................................79 12.2 Overview ..........................................................................................................79 12.3 Timer/Counter Clock Sources ....................................
16.10 ADC Accuracy Definitions .............................................................................123 16.11 ADC Conversion Result .................................................................................125 16.12 Temperature Measurement ...........................................................................125 16.13 Register Description ......................................................................................126 17 debugWIRE On-chip Debug System ...................
20.6 External Interrupt Characteristics ..................................................................158 20.7 Boost Converter Characteristics ....................................................................159 20.8 ADC Characteristics – Preliminary Data ........................................................160 20.9 Parallel Programming Characteristics ...........................................................162 20.10 Serial Programming Characteristics ..................................
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