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BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV

Memory ICs

ID ROM for CRT display

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV

The BR24C21 series are 1kbits serial EEPROMs and support DDC1

and DDC2

interfaces for PLUG&PLAY

displays.

!Features

1) 128 x 8 bits serial EEPROM

2) Operating voltage range (2.5V∼5.5V)

3) Completely implements DDC1

/ DDC2

interface

for monitor identification

Transmit-Only Mode

Recovery Mode

Bi-directional Mode

4) Page write function : 8 bytes

5) Low current consumption

Active (at 5V) : 1.5mA (Typ.)

Standby (at 5V) : 10µA (Typ.)

6) DATA security

Write enable feature

Inhibit to WRITE at low Vcc

7) Compact packages

8) High reliability fine pattern CMOS technology

9) Rewriting possible up to 100,000 times

10) Data can be stored for ten years without corruption

11) Noise filters at SCL, SDA and VCLK pins

!Absolute maximum ratings (Ta=25°C)

Parameter Symbol Limits Unit

Supply voltage −0.3

+6.5 V

Power disssipation

Storage temperature range −65

+125

°C

Operating temperature range

°C

Terminal voltage

−

−40

+85

−0.3

+0.3

Tstg

Topr

∗1

450(SOP8)

800(DIP8)

∗2

450(SOP-J8)

∗3

350(SSOP-B8)

∗1 Degradation is done at 8.0mW/°C for operation above 25°C.

∗2 Degradation is done at 4.5mW/°C for operation above 25°C.

∗3 Degradation is done at 3.5mW/°C for operation above 25°C.

!Recommended operating conditions (Ta=25°C)

Parameter Symbol Limits Unit

Supply voltage

Input voltage V

IN V

0~V

2.5~5.5

Summary of content (11 pages)

PAGE 1
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs ID ROM for CRT display BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV The BR24C21 series are 1kbits serial EEPROMs and support DDC1TM and DDC2TM interfaces for PLUG&PLAY displays. !Features 1) 128 x 8 bits serial EEPROM 2) Operating voltage range (2.5V∼5.
PAGE 2
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs !Block diagram N.C. 1 1kbits EEPROM array 2 N.C. 3 VCC 7 VCLK 6 SCL 5 SDA 8bits 7bits N.C. 8 Address decoder 7bits Data register Slave word address register START STOP Control logic ACK GND High voltage generator 4 Vcc level detecter !Pin assignment VCC VCLK SCL SDA 8 7 6 5 BR24C21 BR24C21F BR24C21FJ BR24C21FV 1 2 3 4 N.C. N.C. N.C. GND !Pin descriptions Pin No. Pin name I/O 1 N.C.
PAGE 3
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs !Electrical characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.5∼5.5V) Parameter Symbol Min. Typ. Max. Unit VIH1 0.7VCC − − V SCL, SDA "HIGH" input volatge1 Conditions "LOW" input volatge1 VIL1 − − 0.3VCC V SCL, SDA "HIGH" input volatge2 VIH2 2.0 − − V VCLK "LOW" input volatge2 VIL2 − − 0.8 V VCLK, VCC≥4.0V "LOW" input volatge3 VIL3 − − 0.2VCC V VCLK, VCC<4.0V "LOW" output volatge VOL − − 0.
PAGE 4
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs !Timing charts SYNCHRONOUS DATA TIMING tR tF tHIGH SCL tHD : STA tSU : DAT tLOW tHD : DAT SDA (IN) tBUF tPD SDA (OUT) SCL tSU : STA tHD : STA tSU : STO SDA START BIT STOP BIT Fig.7 •SDA data is latched into the chip at the rising edge of the SCL clock. •Output data toggles at the falling edge of the SCL clock. WRITE CYCLE TIMING SCL SDA D0 ACK tWR WRITE DATA (n) STOP CONDITION START CONDITION Fig.
PAGE 5
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs !Circuit operation The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV operate in two modes, Transmit-Only Mode and Bi-directional Mode. The devices operate in Transmit-Only Mode when they will power up. In this mode, the devices transmit data on the SDA pin with the VCLK clock. This mode is continued by providing a valid high to low transition on the SCL pin.
PAGE 6
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs (2) Bi-directional Mode 1) Bi-directional Mode and Recovery function •The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid high to low transition on the SCL pin, and the state of SDA is high-impedance. •After a valid high to low transition on the SCL pin, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV begin to count the VCLK clock.
PAGE 7
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs 2) Bi-directional Mode START CONDITION •All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. •The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
PAGE 8
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs ACKNOWLEDGE •Acknowledge is a software convention used to indicate successful data transfers. The master or the slave will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that the eight bits of data has been received. •The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV will respond with an Acknowledge after recognition of a START condition and its slave address.
PAGE 9
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs PAGE WRITE S T A R T SDA LINE W R I T E SLAVE ADDRESS WORD ADDRESS(n) 1 0 1 0 ∗ ∗ ∗ ∗ WA 6 DATA(n+7) DATA(n) WA 0 R A / C W K D7 S T O P D0 D0 A C K A C K A C K VCLK ∗Don't care Fig.16 PAGE WRITE CYCLE TIMING •If the master transmits the next data instead of generating a stop condition in byte write cycle, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV transfer from byte write cycle to page write cycle.
PAGE 10
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs RANDOM READ S T A R T SDA LINE SLAVE ADDRESS W R I T E WORD ADDRESS(n) ∗ 1 0 1 0 ∗ ∗ ∗ S T A R T WA 6 WA 0 R A / C W K SLAVE ADDRESS R E A D 1 0 1 0 ∗ ∗ ∗ A C K S T O P DATA(n) D7 D0 A C K R A / C W K Fig.18 RANDOM READ CYCLE TIMING •Random read operation allows the master to access any memory location. This operation involves a two-step process.
PAGE 11
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV Memory ICs !External dimension (Units : mm) 9.3 ± 0.3 5 5.0 ± 0.2 0.11 5 1 4 1.27 0.4 ± 0.1 0.5 ± 0.1 0°~15° SOP8 4.9 ± 0.2 3.0 ± 0.2 1.27 0.42 ± 0.1 1 4 0.22 ± 0.1 (0.52) 0.15 ± 0.1 6.4 ± 0.3 0.2 ± 0.1 0.45Min. 5 4.4 ± 0.2 3.9 ± 0.2 0.175 1 2 3 4 8 0.1 1.15 ± 0.1 2.54 0.15 8 7 6 5 6.0 ± 0.3 0.3Min. 0.3 ± 0.1 DIP8 1.375 ± 0.1 0.15 ± 0.1 7.62 1.5 ± 0.1 8 4.4 ± 0.2 4 0.51Min. 3.2 ± 0.2 3.4 ± 0.3 1 6.2 ± 0.3 6.5 ± 0.3 8 0.