Manual

ManualsBrandsRainbow Electronics ManualsStorageBR24L32FV-W

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

1/25

8 bit electrically erasable PROM

BR24L32-W / BR24L32F-W / BR24L32FJ-W

BR24L32FV-W

The BR24L32-W series is 2-wire (I

C BUS type) serial EEPROMs which are electrically programmable.

∗

C BUS is a registered trademark of Philips.

Applications

General purpose

Features

1) 4k registers

8 bits serial architecture.

2) Single power supply (1.8V to 5.5V).

3) Two wire serial interface.

4) Automatic erase.

5) 32byte Page Write Mode.

6) Low power consumption.

Write

(5V) : 1.5mA (Typ.)

Read (5V) : 0.2mA (Typ.)

Standby (5V) : 0.1

A (Typ.)

7) DATA security

Write protect feature (WP pin).

Inhibit to WRITE at low V

8) Small package - - - DIP8 / SOP8 / SSOP-B8 pin

9) High reliability EEPROM with Double-Cell structure.

10) High reliability fine pattern CMOS technology.

11) Endurance : 1,000,000 erase / write cycles

12) Data retention : 40 years

13) Filtered inputs in SCL,SDA for noise suppression.

14) Initial data FFh in all address.

Absolute maximum ratings

(Ta=25

Parameter Symbol Limits Unit

Supply voltage −0.3 to +6.5 V

Power dissipation mW

Storage temperature

−65 to +125

°C

Operating temperature

°C

Terminal voltage

−

−40 to +85

−0.3 to V

+0.3

Tstg

Topr

∗1

450(SOP8)

800(DIP8)

∗2

∗3

300(SSOP-B8)

∗1 Degradation is done at 8.0mW/°C for operation above 25°C.

∗2,3 Degradation is done at 4.5mW/°C for operation above 25°C.

∗4 Degradation is done at 3.0mW/°C for operation above 25°C.

450(SOP-J8)

∗4

Summary of content (25 pages)

PAGE 1
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 4k×8 bit electrically erasable PROM BR24L32-W / BR24L32F-W / BR24L32FJ-W BR24L32FV-W The BR24L32-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable. ∗ I2C BUS is a registered trademark of Philips. zApplications General purpose zFeatures 1) 4k registers × 8 bits serial architecture. 2) Single power supply (1.8V to 5.5V). 3) Two wire serial interface. 4) Automatic erase. 5) 32byte Page Write Mode.
PAGE 2
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zRecommended operating conditions (Ta=25°C) Symbol Limits Unit Supply voltage Parameter VCC 1.8 to 5.5 V Input voltage VIN 0 to VCC V zDC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V) Parameter Symbol Min. Typ. Max. Unit Conditions < 5.5V < VCC = 2.5V= < 5.5V < VCC = 2.5V= "HIGH" input volatge 1 VIH1 0.7VCC − − V "LOW" input volatge 1 VIL1 − − 0.
PAGE 3
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zDimension 9.3±0.3 3.2±0.2 5 6.5±0.3 0.51Min. 3.4±0.3 8 1 7.62 4 0.3±0.1 0° ~ 15° 2.54 0.5±0.1 Fig.1(a) PHYSICAL DIMENSION (Units : mm) DIP8 (BR24L32-W) 5.0±0.2 5 1 4 1.5±0.1 0.11 6.2±0.3 4.4±0.2 0.3Min. 8 0.15±0.1 0.1 1.27 0.4±0.1 Fig.1(b) PHYSICAL DIMENSION (Units : mm) SOP8 (BR24L32F-W) 1.375±0.1 0.175 0.45Min. 6.0±0.3 3.9±0.2 4.9±0.2 8 7 65 1234 0.2±0.1 0.1 1.27 0.42±0.1 Fig.
PAGE 4
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zBlock diagram A0 1 32kbit EEPROM array 2 A2 3 VCC 7 WP 6 SCL 5 SDA 8bit 12bit A1 8 Address decoder Data register Slave word address register 12bits START STOP Control logic ACK GND 4 High voltage generator Vcc level detect Fig.2 BLOCK DIAGRAM zPin configuration VCC WP SCL SDA 8 7 6 5 BR24L32-W BR24L32F-W BR24L32FJ-W BR24L32FV-W 1 2 3 4 A0 A1 A2 GND Fig.
PAGE 5
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zAC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V) Parameter Symbol Fast-mode 2.5V < = Vcc < = 5.5V Min. Typ. Max. Standard-mode 1.8V < = Vcc < = 5.5V Min. Typ. Max. Unit Clock frequency fSCL − − 400 − − 100 kHz Data clock "HIGH" period tHIGH 0.6 − − 4.0 − − µs tLOW 1.2 − − 4.7 − − µs tR − − 0.3 − − 1.
PAGE 6
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zSynchronous data timing tR tF tHIGH SCL tHD : STA tSU : DAT tLOW tHD : DAT SDA (IN) tBUF tPD tDH SDA (OUT) SCL tSU : STA tHD : STA tSU : STO SDA START BIT STOP BIT Fig.4 SYNCHRONOUS DATA TIMING •SDA data is latched into the chip at the rising edge of SCL clock. •Output data toggles at the falling edge of SCL clock. zWrite cycle timing SCL SDA D0 ACK tWR WRITE DATA (n) STOP CONDITION START CONDITION Fig.
PAGE 7
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zWP timing SCL DATA (1) SDA D1 DATA (n) D0 ACK ACK tWR STOP BIT WP tSU : WP tHD : WP Fig.6(a) WP TIMING OF THE WRITE OPERATION SCL DATA (1) SDA D1 DATA (n) D0 ACK ACK tHIGH : WP WP Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION •For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in D0 of first byte until the end of tWR. ( See Fig.
PAGE 8
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zDevice operation 1) Start condition (Recognition of start bit) • All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. • The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. (See Fig.
PAGE 9
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 6) Acknowledge • Acknowledge is a software convention used to indicate successful data transfers. The transmitter device will release the bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is µ-COM. When outputting the data in the read operation, it is this device.
PAGE 10
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zByte write S T A R T SDA LINE W R I T E SLAVE ADDRESS 1st WORD ADDRESS ∗ ∗ ∗ ∗ 1 0 1 0 A2 A1 A0 2nd WORD ADDRESS WA 11 R A / C W K DATA WA 0 A C K S T O P D7 D0 A C K A C K WP ∗Don't care Fig.8 BYTE WRITE CYCLE TIMING • By using this command, the data is programmed into the indicated word address. • When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory array.
PAGE 11
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zCurrent read S T A R T SDA LINE R E A D SLAVE ADDRESS 1 0 1 0 A2 A1 A0 S T O P DATA D7 D0 R A / C W K A C K Fig.10 CURRENT READ CYCLE TIMING • In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the internal address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the next word address (n+1).
PAGE 12
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zSequential read S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 A2 A1 A0 DATA(n) D7 R A / C W K S T O P DATA(n+x) D0 D7 A C K A C K D0 A C K Fig.12 SEQUENTIAL READ CYCLE TIMING (Current Read) • If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to transmit the data.
PAGE 13
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs zApplication 1) WP effective timing WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to [ WP effective timing ] as follows. During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective period.
PAGE 14
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 2) Software reset Please execute software reset in case that the device is an unexpected state after power up and / or the command input need to be reset. There are some kinds of software reset. Here we show three types of example as follows. During dummy clock, please release SDA bus (tied to VCC by pull up resistor). During that time, the device may pull the SDA line LOW for Acknowledge or outputting or read data.
PAGE 15
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 3) Acknowledge polling Since the device ignore all input commands during the internal write cycle, no ACK will be returned. When the master send the next command after the write command, if the device returns the ACK, it means that the program is completed. If no ACK id returned, it means that the device is still busy. By using Acknowledge polling, the waiting time is minimized less than tWR=5ms.
PAGE 16
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 4) Command cancellation by start and stop condition During a command input, it is canceled by the successive inputs of start condition and stop condition. (Fig.4) But during ACK or data output, the device may output the SDA line LOW. In such cases, operation of start and stop condition is impossible, so that the reset can’t work. Execute the software reset in the cases.
PAGE 17
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 5) Notes for power supply VCC rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device may not work properly due to an incomplete reset of internal circuit. To prevent this, the device has the feature of P.O.R. and LVCC. In the case of power up, keep the following conditions to ensure functions of P.O.R and LVCC. (1) It is necessary to be “SDA=‘H’ ” and “SCL=’L’ or ‘H’ ”.
PAGE 18
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 6) I / O circuit • Pull up resister of SDA pin The pull up resister is needed because SDA is NMOS open drain. Decide the value of this resister (RPU) properly, by considering VIL, IL characteristics of a controller which control the device and VOH, IOL characteristics of the device. If large RPU is chosen, clock frequency need to be slow. In case of small RPU, the operating current increases.
PAGE 19
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs • The minimum value RPU The minimum value of RPU is determined by following factors. c Meet the condition that VOLMAX=0.4V, IOLMAX=3mA when the device output low on SDA line. VCC − VOL < IOL = RPU RPU < = VCC − VOL IOL d VOLMAX (=0.4V) must be lower than the input LOW level of the controller and the EEPROM including recommended noise margin (0.1VCC). < VIL − 0.1VCC VOLMAX = Examples : VCC=3V, VOL=0.
PAGE 20
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 8) Notes for noise on VCC • About bypass capacitor Noise and surges on power line may cause the abnormal function. It is recommended that the bypass capacitors (0.1µF) are attached on the VCC and GND line beside the device. The attachment of bypass capacitors on the board near by connector is also recommended. IC capacitor 0.01 to 0.
PAGE 21
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs • The maximum value of RS The maximum value of RS is determined by following factors. c SDA rise time determined by RPU and the capacitance of bus line (CBUS ) of SDA must be less than tR. And the other timing must also keep the conditions of the AC timing. d When the device outputs LOW on SDA line, the voltage of the bus A determined by RPU and RS must be lower than the inputs LOW level of the controller, including recommended noise margin (0.
PAGE 22
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 6 5 5 4 SPEC 3 2 Ta=85°C Ta=−40°C Ta=25°C 1 1 L OUTPUT VOLTAGE : VOL (V) 6 L INPUT VOLTAGE : VIL (V) H INPUT VOLTAGE : VIH (V) 10) The special character DATA The following characteristic data are typ. value. 4 Ta=85°C Ta=−40°C Ta=25°C 3 2 1 0.8 0.6 Ta=25°C 0.4 Ta=85°C SPEC 0.2 SPEC 1 3 2 4 5 0 0 6 2 3 4 5 6 1 3 2 4 5 6 SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) L OUTPUT CURRENT : IOL (mA) Fig.
PAGE 23
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 2.5 10000 SPEC 0.5 fSCL=100kHz DATA=AAh 0.3 Ta=25°C Ta=85°C 0.2 0.1 0 0 2 1.5 1 0.5 1 3 2 4 5 0 0 6 1 4 5 6 5 DATA CLK L TIME : tLOW (µs) SPEC2 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 3 2 1 SPEC1 2 3 4 5 4 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 3 2 SPEC1 1 0 0 6 SUPPLY VOLTAGE : VCC (V) Fig.
PAGE 24
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W SPEC2 200 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE SPEC1 100 0 Ta=85°C Ta=25°C Ta=−40°C −100 −200 0 1 2 3 4 5 6 300 SPEC2 200 SPEC1 −200 0 1 Ta=−40°C 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.35 Input data setup time tSU:DAT(HIGH) Fig.
PAGE 25
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W Memory ICs 0.6 0.5 Ta=−40°C 0.4 Ta=25°C 0.3 Ta=85°C 0.2 0.1 SPEC1,2 0 0 1 2 3 4 5 0.5 0.4 0.3 Ta=−40°C 0.2 Ta=25°C Ta=85°C 0.1 SPEC1,2 0 0 6 1 2 3 4 5 6 0.4 Ta=−40°C 0.3 Ta=25°C Ta=85°C 0.2 0.1 SPEC1,2 0 0 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.44 Noise spike width tI (SCL H) Fig.45 Noise spike width tI (SCL L) Fig.46 Noise spike width tI (SDA H) 0.2 0.4 Ta=−40°C Ta=25°C Ta=85°C 0.2 0.