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Standard ICs

Dual 4-bit static shift register

BU4015B / BU4015BF

The BU4015B and BU4015BF are 4-stage static shift registers, each consisting of two circuits.

The D flip-flops for each stage share a common reset input, enabling external asynchronous reset at any point.

Also, the flip-flops at each stage are triggered by the rising edge of the clock input.

“H” level reset input resets the contents of all stages to “L”, regardless of the clock and data input, and sets data out-

puts Q0 to Q3 to “L”.

•

Features

1) Low power dissipation.

2) Wide range of operating power supply voltages.

3) High input impedance.

4) High fan-out.

5) Direct drive of 2 L-TTL inputs and 1 LS-TTL input.

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Block diagram

Q1A

Q0A

Q2B

RESET

CLOCK

VDD

Q0B

Q1B

Q2B

Q3A

RESET

CLOCK

Q3 Q2 Q1

CL R D

0 Q1 Q2

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Logic circuit diagram

0 Q1 Q2 Q3

CLOCK

RESET

•

Truth table

CLOCK D RESET Q

LL LQ

HL HQ

X L No Change

XXH L L L

X : Irrelevant

Summary of content (4 pages)

PAGE 1
Standard ICs Dual 4-bit static shift register BU4015B / BU4015BF The BU4015B and BU4015BF are 4-stage static shift registers, each consisting of two circuits. The D flip-flops for each stage share a common reset input, enabling external asynchronous reset at any point. Also, the flip-flops at each stage are triggered by the rising edge of the clock input. “H” level reset input resets the contents of all stages to “L”, regardless of the clock and data input, and sets data outputs Q0 to Q3 to “L”.
PAGE 2
Standard ICs BU4015B / BU4015BF •Absolute maximum ratings (V SS = 0V, Ta = 25°C) Parameter Symbol Limits Power supply voltage VDD – 0.3 ~ + 18 V Power dissipation Pd 1000 (DIP), 500 (SOP) mW Operating temperature Topr – 40 ~ + 85 °C Storage temperature Tstg – 55 ~ + 150 °C – 0.3 ~ VDD + 0.3 V Input voltage VIN characteristics •DCElectrical characteristics (unless otherwise noted, Ta = 25°C, V Parameter Input high level voltage Input low level voltage = 0V) Symbol Min. 3.
PAGE 3
Standard ICs BU4015B / BU4015BF Switching characteristics (unless otherwise noted, Ta = 25°C, VSS = 0V, CL = 50pF) Parameter Output rise time Output fall time Propagation delay time, CLOCK, D→Q Propagation delay time, RESET to Q Setup time Minimum clock pulse width Minimum reset pulse width Maximum clock frequency Maximum clock rise time and fall time Input capacitance Symbol tTLH tTHL tPLH tPHL tPLH tPHL tsu tWH (CLK) tWH (R) f (CLK) Max. tr (CLK) tf (CLK) CIN Min. Typ. Max.
PAGE 4
Standard ICs BU4015B / BU4015BF •Measurement circuits VDD 20ns 20ns tSU tSU D D P. G. 2 Q0 20ns Q1 tWH Q2 CL R P. G. 1 20ns CLOCK tWH tPLH tPHL 90% Q0 Q3 CL VSS CL CL tTLH CL tPHL 50% 10% 50% tTHL 20ns RESET 10% GND 20ns 90% 50% 10% tWH (R) Fig.1 Switching characteristics measurement circuit Fig.