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Standard ICs

8-bit compatible shift / store register

BU4094BC / BU4094BCF / BU4094BCFV

The BU4094BC, BU4094BCF, and BU4094BCFV are shift / store registers, each consisting of an 8-bit register and

an 8-bit latch.

As the data in the shift register can be latched by an asynchronous strobe input, it is possible to hold the output in

the data transfer mode.

The tri-state parallel output can be connected directly with an 8-bit bus line.

These registers are suitable for in-line / parallel data conversion, data receivers and other similar applications.

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Logic circuit diagram

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Truth table

8-STAGE

SHIFT REGISTER

CLOCK

SERIAL

Q'S

SERIAL

OUTPUT

PARALLEL OUTPUTS

8-BIT

LATCHES

STROBE

3-STATE

OUTPUTS

OUTPUT

ENABLE

Q1 Q8

CLOCK

OUTPUT

ENABLE

STROBE

Parallel output Serial output

1 Qn QS

HH L L Q7 NC

HH H H Q

7 NC

HL XNCNCQ

7 NC

LX X ZZQ

7 NC

HX XNCNCNCQ

LX X ZZNCQS

Qn-1

SERIAL IN

NC: No Change Z: High Impedance X: Irrelevant

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Block diagram

SERIAL

STROBE

CLOCK

OUTPUT

ENABLE

Q'S

Summary of content (5 pages)

PAGE 1
Standard ICs 8-bit compatible shift / store register BU4094BC / BU4094BCF / BU4094BCFV The BU4094BC, BU4094BCF, and BU4094BCFV are shift / store registers, each consisting of an 8-bit register and an 8-bit latch. As the data in the shift register can be latched by an asynchronous strobe input, it is possible to hold the output in the data transfer mode. The tri-state parallel output can be connected directly with an 8-bit bus line.
PAGE 2
Standard ICs BU4094BC / BU4094BCF / BU4094BCFV •Absolute maximum ratings (Ta = 25°C) Symbol Limits Unit Power supply voltage Parameter VDD – 0.5 ~ + 20 V Power dissipation Pd 1000 (DIP), 500 (SOP) 400 (SSOP) mW Operating temperature Topr – 40 ~ + 85 °C Storage temperature Tstg – 55 ~ + 150 °C – 0.5 ~ VDD + 0.
PAGE 3
Standard ICs BU4094BC / BU4094BCF / BU4094BCFV Switching characteristics (unless otherwise noted, VSS = 0V, Ta = 25°C, CL = 50pF) Parameter Symbol Output rise time tTLH Output fall time tTHL Propagation delay time, CLOCK to Qs tPLH tPHL Propagation delay time, CLOCK to Qs tPLH tPHL Propagation delay time, CLOCK to Qn tPLH tPHL Propagation delay time, STROBE to Qn tPLH tPHL 3-state propagation delay time, Output Enable to Qn tPHZ tPZH 3-state propagation delay time, Output Enable to Qn tPL
PAGE 4
Standard ICs BU4094BC / BU4094BCF / BU4094BCFV •Measurement circuits VDD OUTPUT ENABLE OUTPUT ENABLE OUTPUT DATA 50pF 50pF STROBE P.G. CLOCK GND A: tPLZ, tPZL B: tPHZ, tPZH CLOCK GND Fig. 2 3-state delay time Fig. 1 Switching waveform tW tr 90% 50% CLOCK 50% 50% 50% tf 90% 50% 10% tSU DATA tH 50% 50% tWH 50% STROBE OUTPUT ENABLE 50% tPLH tPHL tTLH tTHL 50% tPHZ tPHL 50% Q's Fig.
PAGE 5
Standard ICs BU4094BC / BU4094BCF / BU4094BCFV •External dimensions (Units: mm) BU4094BC BU4094BCF 10.0 ± 0.2 19.4 ± 0.3 8 6.2 ± 0.3 0.51Min. 0.3 ± 0.1 0.5 ± 0.1 0° ~ 15° 0.11 1.5 ± 0.1 3.2 ± 0.2 4.25 ± 0.3 7.62 2.54 9 1 8 1.27 0.4 ± 0.1 0.15 ± 0.1 1 16 4.4 ± 0.2 9 6.5 ± 0.3 16 0.3Min. 0.15 DIP16 SOP16 BU4094BCFV 1 8 4.4 ± 0.2 9 0.65 0.15 ± 0.1 1.15 ± 0.1 0.1 6.4 ± 0.3 5.0 ± 0.2 16 0.22 ± 0.1 0.3Min. 0.