User Manual
Functional Description (Continued)
2.5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input sig-
nal that does not go to ground) this new zero reference
should be properly adjusted first. A V
IN
(
a
) voltage that
equals this desired zero reference plus (/2 LSB (where the
LSB is calculated for the desired analog span, 1 LSB
e
ana-
log span/256) is applied to pin 6 and the zero reference
voltage at pin 7 should then be adjusted to just obtain the
00
HEX
to 01
HEX
code transition.
The full-scale adjustment should then be made (with the
proper V
IN
(
b
) voltage applied) by forcing a voltage to the
V
IN
(
a
) input which is given by:
V
IN
(
a
)fsadj
e
V
MAX
b
1.5
Ð
(V
MAX
b
V
MIN
)
256
(
,
where:
V
MAX
e
The high end of the analog input range
and
V
MIN
e
the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The V
REF
/2 (or V
CC
) voltage is then adjusted to provide a
code change from FE
HEX
to FF
HEX
. This completes the ad-
justment procedure.
2.6 Clocking Option
The clock for the A/D can be derived from the CPU clock or
an external RC can be added to provide self-clocking. The
CLK IN (pin 4) makes use of a Schmitt trigger as shown in
Figure 6
.
f
CLK
j
1
1.1 RC
R
j
10 kX
TL/H/5671–17
FIGURE 6. Self-Clocking the A/D
Heavy capacitive or DC loading of the clock R pin should be
avoided as this will disturb normal converter operation.
Loads less than 50 pF, such as driving up to 7 A/D convert-
er clock inputs from a single clock R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize
the loading on the clock R pin (do not use a standard TTL
buffer).
2.7 Restart During a Conversion
If the A/D is restarted (CS
and WR go low and return high)
during a conversion, the converter is reset and a new con-
version is started. The output data latch is not updated if the
conversion in process is not allowed to be completed, there-
fore the data of the previous conversion remains in this
latch. The INTR
output simply remains at the ‘‘1’’ level.
2.8 Continuous Conversions
For operation in the free-running mode an initializing pulse
should be used, following power-up, to ensure circuit opera-
tion. In this application, the CS
input is grounded and the
WR
input is tied to the INTR output. This WR and INTR
node should be momentarily forced to logic low following a
power-up cycle to guarantee operation.
2.9 Driving the Data Bus
This MOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuitry, which is tied to the data
bus, will add to the total capacitive loading, even in TRI-
STATE (high impedance mode). Backplane bussing also
greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to
handle this problem. Basically, the capacitive loading of the
data bus slows down the response time, even though DC
specifications are still met. For systems operating with a
relatively slow CPU clock frequency, more time is available
in which to establish proper logic levels on the bus and
therefore higher capacitive loads can be driven (see typical
characteristics curves).
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock extending circuits (6800).
Finally, if time is short and capacitive loading is high, exter-
nal bus drivers must be used. These can be TRI-STATE
buffers (low power Schottky such as the DM74LS240 series
is recommended) or special higher drive current products
which are designed as bus drivers. High current bipolar bus
drivers with PNP inputs are recommended.
2.10 Power Supplies
Noise spikes on the V
CC
supply line can cause conversion
errors as the comparator will respond to this noise. A low
inductance tantalum filter capacitor should be used close to
the converter V
CC
pin and values of 1 mF or greater are
recommended. If an unregulated voltage is available in the
system, a separate LM340LAZ-5.0, TO-92, 5V voltage regu-
lator for the converter (and other analog circuitry) will greatly
reduce digital noise on the V
CC
supply.
2.11 Wiring and Hook-Up Precautions
Standard digital wire wrap sockets are not satisfactory for
breadboarding this A/D converter. Sockets on PC boards
can be used and all logic signal wires and leads should be
grouped and kept as far away as possible from the analog
signal leads. Exposed leads to the analog inputs can cause
undesired digital noise and hum pickup, therefore shielded
leads may be necessary in many applications.
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