User Manual

Functional Description (Continued)
SAMPLE PROGRAM FOR
FIGURE 15 ADC0801– MC6820 PIA INTERFACE
0010 CE 00 38 DATAIN LDX #$0038 ; Upon IRQ
low CPU
0013 FF FF F8 STX $FFF8 ; jumps to 0038
0016 B6 80 06 LDAA PIAORB ; Clear possible IRQ
flags
0019 4F CLRA
001A B7 80 07 STAA PIACRB
001D B7 80 06 STAA PIAORB ; Set Port B as input
0020 0E CLI
0021 C6 34 LDAB #$34
0023 86 3D LDAA #$3D
0025 F7 80 07 CONVRT STAB PIACRB ; Starts ADC0801
0028 B7 80 07 STAA PIACRB
002B 3E WAI ; Wait for interrupt
002C DE 40 LDX TEMP1
002E 8C 02 0F CPX #$020F ; Is final data stored?
0031 27 0F BEQ ENDP
0033 08 INX
0034 DF 40 STX TEMP1
0036 20 ED BRA CONVRT
0038 DE 40 INTRPT LDX TEMP1
003A B6 80 06 LDAA PIAORB ; Read data in
003D A7 00 STAA X ; Store it at X
003F 3B RTI
0040 02 00 TEMP1 FDB $0200 ; Starting address for
; data storage
0042 CE 02 00 ENDP LDX #$0200 ; Reinitialize TEMP1
0045 DF 40 STX TEMP1
0047 39 RTS ; Return from subroutine
PIAORB EQU $8006 ; To user’s program
PIACRB EQU $8007
The following schematic and sample subroutine (DATA IN)
may be used to interface (up to) 8 ADC0801’s directly to the
MC6800 CPU. This scheme can easily be extended to allow
the interface of more converters. In this configuration the
converters are (arbitrarily) located at HEX address 5000 in
the MC6800 memory space. To save components, the
clock signal is derived from just one RC pair on the first
converter. This output drives the other A/Ds.
All the converters are started simultaneously with a STORE
instruction at HEX address 5000. Note that any other HEX
address of the form 5XXX will be decoded by the circuit,
pulling all the CS
inputs low. This can easily be avoided by
using a more definitive address decoding scheme. All the
interrupts are ORed together to insure that all A/Ds have
completed their conversion before the microprocessor is in-
terrupted.
The subroutine, DATA IN, may be called from anywhere in
the user’s program. Once called, this routine initializes the
CPU, starts all the converters simultaneously and waits for
the interrupt signal. Upon receiving the interrupt, it reads the
converters (from HEX addresses 5000 through 5007) and
stores the data successively at (arbitrarily chosen) HEX ad-
dresses 0200 to 0207, before returning to the user’s pro-
gram. All CPU registers then recover the original data they
had before servicing DATA IN.
5.2 Auto-Zeroed Differential Transducer Amplifier
and A/D Converter
The differential inputs of the ADC0801 series eliminate the
need to perform a differential to single ended conversion for
a differential transducer. Thus, one op amp can be eliminat-
ed since the differential to single ended conversion is pro-
vided by the differential input of the ADC0801 series. In gen-
eral, a transducer preamp is required to take advantage of
the full A/D converter input dynamic range.
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