User Manual
Functional Description (Continued)
SAMPLE PROGRAM FOR
FIGURE 16
INTERFACING MULTIPLE A/Ds IN AN MC6800 SYSTEM
ADDRESS HEX CODE MNEMONICS COMMENTS
0033 A7 00 STAA X ; Store data at X
0035 8C 02 07 CPX #$0207 ; Have all A/D’s been read?
0038 27 05 BEQ RETURN ; Yes: branch to RETURN
003A 08 INX ; No: increment X by one
003B DF 42 STX INDEX2 ; X
x
INDEX2
003D 20 EB BRA INTRPT ; Branch to 002A
003F 3B RETURN RTI
0040 50 00 INDEX1 FDB $5000 ; Starting address for A/D
0042 02 00 INDEX2 FDB $0200 ; Starting address for data storage
0044 00 00 TEMP FDB $0000
Note 1: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program.
For amplification of DC input signals, a major system error is
the input offset voltage of the amplifiers used for the
preamp.
Figure 17
is a gain of 100 differential preamp
whose offset voltage errors will be cancelled by a zeroing
subroutine which is performed by the INS8080A microproc-
essor system. The total allowable input offset voltage error
for this preamp is only 50 mV for (/4 LSB error. This would
obviously require very precise amplifiers. The expression for
the differential output voltage of the preamp is:
V
O
e
[
V
IN
(
a
)
b
V
IN
(
b
)
]
Ð
1
a
2R2
R1
(
a
X ä YX ä Y
SIGNAL GAIN
(V
OS
2
b
V
OS
1
b
V
OS
3
g
I
X
R
X
)
#
1
a
2R2
R1
J
X ä YX ä Y
DC ERROR TERM GAIN
where I
X
is the current through resistor R
X
. All of the offset
error terms can be cancelled by making
g
I
X
R
X
e
V
OS1
a
V
OS3
b
V
OS2
. This is the principle of this auto-zeroing
scheme.
The INS8080A uses the 3 I/O ports of an INS8255 Pro-
gramable Peripheral Interface (PPI) to control the auto zero-
ing and input data from the ADC0801 as shown in
Figure 18
.
The PPI is programmed for basic I/O operation (mode 0)
with Port A being an input port and Ports B and C being
output ports. Two bits of Port C are used to alternately open
or close the 2 switches at the input of the preamp. Switch
SW1 is closed to force the preamp’s differential input to be
zero during the zeroing subroutine and then opened and
SW2 is then closed for conversion of the actual differential
input signal. Using 2 switches in this manner eliminates con-
cern for the ON resistance of the switches as they must
conduct only the input bias current of the input amplifiers.
Output Port B is used as a successive approximation regis-
ter by the 8080 and the binary scaled resistors in series with
each output bit create a D/A converter. During the zeroing
subroutine, the voltage at V
x
increases or decreases as re-
quired to make the differential output voltage equal to zero.
This is accomplished by ensuring that the voltage at the
output of A1 is approximately 2.5V so that a logic ‘‘1’’ (5V)
on any output of Port B will source current into node V
X
thus
raising the voltage at V
X
and making the output differential
more negative. Conversely, a logic ‘‘0’’ (0V) will pull current
out of node V
X
and decrease the voltage, causing the differ-
ential output to become more positive. For the resistor val-
ues shown, V
X
can move
g
12 mV with a resolution of 50
mV, which will null the offset error term to (/4 LSB of full-
scale for the ADC0801. It is important that the voltage levels
that drive the auto-zero resistors be constant. Also, for sym-
metry, a logic swing of 0V to 5V is convenient. To achieve
this, a CMOS buffer is used for the logic output signals of
Port B and this CMOS package is powered with a stable 5V
source. Buffer amplifier A1 is necessary so that it can
source or sink the D/A output current.
27